From bcae63bb27e513e90d22477029017e9fe0971bff Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Wed, 25 Dec 2019 14:00:27 +0800 Subject: arm64: dts: layerscape: apply dma-coherent for dwc3 nodes Since dwc3 cache type has been set to cacheable, apply dma-coherent to all dwc3 nodes accordingly. Note: For LS1043A and LS1046A, since QE-HDLC still doesn't support dma-coherent, we cannot directly revert cd1a4f3c (sdk: dts: ls104x move dma-coherent from soc to its child nodes) to recover dma-coherent for soc. Signed-off-by: Ran Wang --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 7e5e4a2fbd7e..3218d69df3a6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -874,6 +874,7 @@ snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; -- cgit v1.2.3