From c1e14884a3bdcc64cdf077dad38f5ed4123d1de3 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 8 Nov 2019 10:22:31 +0800 Subject: MLK-22930 ARM64: dts: change the source clock rate of usdhc1 for imx8qxp/imx8qm On imx8qxp and imx8qm mek board, usdhc1 is for eMMC usage, and will work at HS400 mode, this HS400 mode will work at 200MHz, and will default divide 2 from source clock(IMX_SC_R_SDHC_0), which mean we need to config the source clock to 400MHz at least. Before this patch, HS400 mode only work at 100MHz, and will meet some timeout issue when do system suspend/resume, due to our HS400 related timing setting is based on the 200MHz. Also, HS400 work at 100MHz will impact the performance. Signed-off-by: Haibo Chen Acked-by: Leonard Crestez Tested-by: Anson Huang --- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index a8083e0531ee..f23d45f1ee87 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -73,7 +73,7 @@ conn_subsys: bus@5b000000 { <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; -- cgit v1.2.3