From f9a192b4bfd814ee797a80e41730a18f36c9651f Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Thu, 18 Jul 2019 17:17:29 +0800 Subject: arm64: dts: imx8: conn: fully switched to new clk binding fully switched to new clk binding Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 57 ++++++++++++++++--------- 1 file changed, 37 insertions(+), 20 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 8546456afa36..6b9d64125bad 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -41,7 +41,7 @@ conn_subsys: bus@5b000000 { interrupts = ; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; - clocks = <&conn_lpcg IMX_CONN_LPCG_USB2_AHB_CLK>; + clocks = <&usb2_lpcg 0>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -59,7 +59,7 @@ conn_subsys: bus@5b000000 { compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x5b100000 0x1000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_USB2_PHY_IPG_CLK>; + clocks = <&usb2_lpcg 1>; power-domains = <&pd IMX_SC_R_USB_0_PHY>; status = "disabled"; }; @@ -124,8 +124,8 @@ conn_subsys: bus@5b000000 { <&enet0_lpcg 0>, <&enet0_lpcg 1>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; - assigned-clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, - <&clk IMX_CONN_ENET0_REF_DIV>; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -145,8 +145,8 @@ conn_subsys: bus@5b000000 { <&enet1_lpcg 0>, <&enet1_lpcg 1>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; - assigned-clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, - <&clk IMX_CONN_ENET1_REF_DIV>; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -200,14 +200,17 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; bit-offset = <0 4 8 12 16 20>; - clock-output-names = "enet0_timer_clk", - "enet0_txc_sampling_clk", - "enet0_ahb_clk", - "enet0_rgmii_txc_clk", - "enet0_ipg_clk", - "enet0_ipg_s_clk"; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_rgmii_txc_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_0>; }; @@ -217,14 +220,28 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; bit-offset = <0 4 8 12 16 20>; - clock-output-names = "enet1_timer_clk", - "enet1_txc_sampling_clk", - "enet1_ahb_clk", - "enet1_rgmii_txc_clk", - "enet1_ipg_clk", - "enet1_ipg_s_clk"; + clock-output-names = "enet1_lpcg_timer_clk", + "enet1_lpcg_txc_sampling_clk", + "enet1_lpcg_ahb_clk", + "enet1_lpcg_rgmii_txc_clk", + "enet1_lpcg_ipg_clk", + "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + bit-offset = <24 28>; + clock-output-names = "usboh3_ahb_clk", + "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; }; -- cgit v1.2.3