From 6cc83bcf29b4ac89780ec5aede662c4613fdf132 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 20 Aug 2019 17:33:04 +0800 Subject: arm64: imx8-ss-dc0/1.dtsi: Add dc0/1_displ_lpcg clocks This patch adds dc0/1_displ_lpcg clocks to DC0/1 subsystem device trees. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index d18956d5c284..85df8651906c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -30,6 +30,17 @@ dc0_subsys: bus@56000000 { clock-output-names = "dc0_axi_ext_clk"; }; + dc0_disp_lpcg: clock-controller@56010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; + dc0_dpr0_lpcg: clock-controller@56010018 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56010018 0x4>; -- cgit v1.2.3