From dd8ddfd6469f80183803021818779497851a6ec0 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 22 Nov 2019 17:54:22 +0800 Subject: arm64: imx8-ss-dc1.dtsi: Correct display LPCG clocks in DC1 subsystem This patch corrects display LPCG clocks in DC1 subsystem by s/dc0_disp_lpcg/dc1_disp_lpcg/. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index af6a589aca96..3702975f3d96 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -468,7 +468,7 @@ dc1_subsys: bus@57000000 { <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>, - <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; + <&dc1_disp_lpcg 0>, <&dc1_disp_lpcg 1>; clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1", "disp0_lpcg", "disp1_lpcg"; power-domains = <&pd IMX_SC_R_DC_1>, <&pd IMX_SC_R_DC_1_PLL_0>, -- cgit v1.2.3