From 6b36a7243acb2d833cfd53f15c84c3e44aa23cec Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 7 Apr 2020 11:41:33 +0800 Subject: MLK-24012-04 arm64: dts: add imx8qxp pcie ep support Add the iMX8QXP PCIe EP mode, and verified on MEK board. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan --- arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 916b18bb925f..c6629e048777 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -131,4 +131,34 @@ hsio_subsys: bus@5f000000 { local-addr = <0x80000000>; status = "disabled"; }; + + pcieb_ep: pcie_ep@0x5f010000 { + compatible = "fsl,imx8qxp-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */ + <0x70000000 0x10000000>; + reg-names = "regs", "hsio", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per"; + power-domains = <&pd IMX_SC_R_PCIE_B>, + <&pd IMX_SC_R_SERDES_1>, + <&pd IMX_SC_R_HSIO_GPIO>; + power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; + fsl,max-link-speed = <3>; + hsio-cfg = ; + local-addr = <0x80000000>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; }; -- cgit v1.2.3