From f1e4bfdabb26e4a14aa1ddd5d9360c15e9eba576 Mon Sep 17 00:00:00 2001 From: "Guoniu.zhou" Date: Wed, 25 Mar 2020 15:38:24 +0800 Subject: MLK-23315-2: arm64: dts: imx8: add i2c and irqsteer device node for CI_PI ss Add i2c controller and irqsteer device node for CI_PI subsystem of iMX8QXP Signed-off-by: Guoniu.zhou Reviewed-by: Robby Cai --- arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index 5dce31da1111..c7be9fdc4df0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -254,6 +254,22 @@ img_subsys: bus@58000000 { status = "disabled"; }; + irqsteer_parallel: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&clk_dummy>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + gpio0_mipi_csi0: gpio@58222000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x58222000 0x1000>; @@ -281,6 +297,20 @@ img_subsys: bus@58000000 { status = "disabled"; }; + i2c0_parallel: i2c@58266000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_parallel>; + clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; + status = "disabled"; + }; + gpio0_mipi_csi1: gpio@58242000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x58242000 0x1000>; -- cgit v1.2.3