From 910929b7674d7fd55f4283da629e332b1b0de5e5 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Mon, 13 Jul 2020 12:34:12 -0500 Subject: MLK-24403: dts: arm64: freescale: imx8mm ab2 update to cpld s1 v3.4 Update SAI routing options to match CPLD firmware version: ab2_s1_v3.4_20200630 Signed-off-by: Adrian Alonso Reviewed-by: Viorel Suman --- arch/arm64/boot/dts/freescale/imx8mm-ab2.dts | 31 ++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mm-ab2.dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts index 7681b3020cc1..a09d3aac7a78 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts @@ -185,7 +185,7 @@ sound-ak5552 { compatible = "fsl,imx-audio-ak5552"; model = "ak5552-audio"; - audio-cpu = <&sai3>; + audio-cpu = <&sai5>; audio-codec = <&ak5552>; }; @@ -264,6 +264,21 @@ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + status = "disabled"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; status = "okay"; }; @@ -564,7 +579,7 @@ ak5552: ak5552@13 { compatible = "asahi-kasei,ak5552"; reg = <0x13>; - reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; AVDD-supply = <®_adc_avdd_5v0>; DVDD-supply = <®_adc_dvdd_3v3>; }; @@ -719,6 +734,18 @@ >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 -- cgit v1.2.3