From 07364a7aa5ca134f17facb177807575eb460d3c6 Mon Sep 17 00:00:00 2001 From: Robby Cai Date: Tue, 28 Apr 2020 12:29:04 +0800 Subject: MLK-23600-2 arm64: dts: imx8mp: set media axi/apb clock to desired value set media axi clock to 500MHz and apb clock to 200MHz for 4K Signed-off-by: Robby Cai Reviewed-by: Guoniu.zhou --- .../arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts index 87677156dda2..b23b80664b11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts @@ -85,14 +85,28 @@ &mipi_csi_0 { clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; }; &mipi_csi_1 { clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; }; -- cgit v1.2.3