From 1ad71e29f5e58bcf3c128ffdce6f4caece0c6768 Mon Sep 17 00:00:00 2001 From: Robby Cai Date: Thu, 24 Dec 2020 20:41:57 +0800 Subject: MLK-23600-2 Update ISP and Dewarp clock and power update ISP and Dewarp clock and power Signed-off-by: Robby Cai Reviewed-by: Guoniu.zhou (cherry picked from commit e6031680ba2d67a6961a5da5fc68a913962c66d2) (cherry picked from commit f5390f2bcbc7cb9fab29605fc2d3cb61373a5800) Signed-off-by: Andrey Zhizhikin --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 133a45f22ffe..daac9bbfc22b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1810,8 +1810,10 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e10000 0x10000>; interrupts = ; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; @@ -1824,8 +1826,10 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e20000 0x10000>; interrupts = ; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; @@ -1838,6 +1842,14 @@ compatible = "fsl,imx8mp-dwe"; reg = <0x32e30000 0x10000>; interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; id = <0>; status = "disabled"; }; @@ -1846,6 +1858,14 @@ compatible = "fsl,imx8mp-dwe"; reg = <0x32e30000 0x10000>; interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; id = <1>; status = "disabled"; }; -- cgit v1.2.3