From 6a759a0628c13be3d7347fdbeb5721a34eed3bd8 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Wed, 11 Nov 2020 16:53:21 +0800 Subject: MLK-24998-5 arm64: dts: imx8mp: correct assigned-clock-rates for lcdif2 According to i.MX8MP Architecture Defition Document, the maximum clock rate comes generated by 'ccm_media_disp2_pix_clk_root' is 160MHz, so 1039.5MHz clock rate is not supported. And besides, this clock rate will be set to the matched rate with display mode in lcdif driver, so it is not necessary to set its rate in its assigned-clock-rates property, and just leave it to be 0. Signed-off-by: Fancy Fang Reviewed-by: Liu Ying (cherry picked from commit 0e3556f282466e6b91def024afc815ef77733161) --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 496c4c77d3dd..4bb946f10c53 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1478,7 +1478,7 @@ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <1039500000>, <500000000>, <200000000>; + assigned-clock-rates = <0>, <500000000>, <200000000>; interrupts = ; power-domains = <&mediamix_pd>; status = "disabled"; -- cgit v1.2.3