From 187d81ea3bf68171a21baf33e6faf2c5df24f341 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 29 Nov 2019 16:57:52 +0800 Subject: LF-270 ARM64: dts: imx8mq.dtsi: set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate Need to set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate to 266MHz, to make clock align, otherwise USDHC oparation will has issue. Signed-off-by: Haibo Chen --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index f71ffd231109..5ded5dd003ec 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -623,6 +623,8 @@ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; }; src: reset-controller@30390000 { -- cgit v1.2.3