From 16a284f19133249c5b20c8ca7f6ecf258b868a91 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Fri, 26 Jul 2019 16:17:09 +0800 Subject: arch: arm64: imx8qm: add CAN node in devicetree Add CAN node for imx8qm in devicetree. Signed-off-by: Joakim Zhang --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 0b8afd467595..437d4981c2c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -15,6 +15,50 @@ clock-output-names = "uart4_lpcg_baud_clk", "uart4_lpcg_ipg_clk"; }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + bit-offset = <0 16 20>; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = <1>; }; &lpuart0 { -- cgit v1.2.3