From 51c4b191a8a3bdbfb5abfea956f767f19192f148 Mon Sep 17 00:00:00 2001
From: Robin Gong <yibin.gong@nxp.com>
Date: Mon, 5 Aug 2019 21:58:04 +0800
Subject: ARM64: imx8qm: add edma device nodes

edma devices are slight different with i.mx8qxp, such as different
edma2 called on i.mx8qm while edma0 called on i.mx8qxp for the same
edma address map. Besides, dma channel used by audio/uart may be
different with i.mx8qxp too.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 47 ++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi')

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index bda133763621..7f3cd564c0d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -65,12 +65,59 @@
 	compatible = "fsl,imx8qm-lpspi", "fsl,imx7ulp-spi";
 };
 
+/* edma0 called in imx8qm RM with the same address in edma2 of imx8qxp */
+&edma2 {
+	reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */
+	      <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */
+	      <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */
+	      <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */
+	      <0x5a2c0000 0x10000>, /* channel12 UART0 rx */
+	      <0x5a2d0000 0x10000>, /* channel13 UART0 tx */
+	      <0x5a2e0000 0x10000>, /* channel14 UART1 rx */
+	      <0x5a2f0000 0x10000>, /* channel15 UART1 tx */
+	      <0x5a300000 0x10000>, /* channel16 UART2 rx */
+	      <0x5a310000 0x10000>, /* channel17 UART2 tx */
+	      <0x5a320000 0x10000>, /* channel18 UART3 rx */
+	      <0x5a330000 0x10000>, /* channel19 UART3 tx */
+	      <0x5a340000 0x10000>, /* channel20 UART4 rx */
+	      <0x5a350000 0x10000>; /* channel21 UART4 tx */
+	#dma-cells = <3>;
+	dma-channels = <14>;
+	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
+			  "edma0-chan6-rx", "edma0-chan7-tx",
+			  "edma0-chan12-rx", "edma0-chan13-tx",
+			  "edma0-chan14-rx", "edma0-chan15-tx",
+			  "edma0-chan16-rx", "edma0-chan17-tx",
+			  "edma0-chan18-rx", "edma0-chan19-tx",
+			  "edma0-chan20-rx", "edma0-chan21-tx";
+	status = "okay";
+};
+
 &lpuart0 {
 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 };
 
 &lpuart1 {
 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+	power-domains = <&pd IMX_SC_R_UART_1>,
+			<&pd IMX_SC_R_DMA_0_CH14>,
+			<&pd IMX_SC_R_DMA_0_CH15>;
+	dmas = <&edma2 15 0 0>,
+	       <&edma2 14 0 1>;
 };
 
 &lpuart2 {
-- 
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