From 7362764b2043dacc4700238eec0c8235915c5cb8 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Thu, 11 Feb 2021 10:23:17 +0200 Subject: arm64: dts: colibri-imx8x: add atmel mxt device node Overlays should be as simple as possibles, so return back the node for the Atmel MXT touchscreen controller. The common scheme of pingroups for atmel mxt ts: pinctrl_atmel_conn - uses 107/106 pins for INT/Reset signals; pinctrl_atmel_adap - uses 28/30 pins for INT/Reset signals. Fixed: a10fe657dfa7 ("ARM64: dts: colibri-imx8x: Add Atmel touchscreen") Signed-off-by: Oleksandr Suvorov --- arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 06acbe833c96..696c1b3e15ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -529,6 +529,18 @@ clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; }; &imx8_gpu_ss { @@ -558,6 +570,26 @@ >; }; + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_conn: mxt-ts-connector { + fsl,pins = < + IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021 /* SODIMM 107 */ + IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* SODIMM 106 */ + >; + }; + + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pingroup conflicts with pingroups + * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them + * simultaneously. + */ + pinctrl_atmel_adap: mxt-ts-adapter { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021 /* SODIMM 28 */ + IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21 /* SODIMM 30 */ + >; + }; + pinctrl_can_int: can-int-grp { fsl,pins = < IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ -- cgit v1.2.3