From 0e1ccc89bbaab36bfe96431aafecdb7357a24e81 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 30 Oct 2019 14:37:11 +0800 Subject: arm64: dts: imx8qxp-lpddr4-val: support audio sound card Add support audio sound card (ESAI/ASRC/AMIX/CS42888/MQS) Signed-off-by: Shengjiu Wang --- .../dts/freescale/imx8qxp-lpddr4-val-spdif.dts | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts') diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts new file mode 100644 index 000000000000..81ec0d0e9b98 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&spdif0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; -- cgit v1.2.3