From 042f030b9014fc694f9e6352865febb4c6e22716 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Thu, 18 Jul 2019 22:40:36 +0800 Subject: arm64: dts: imx8: gpu0: move into a separate ss dtsi move gpu0 changes into a separate ss dtsi Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 +----------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index ee452eab7ce1..a5fb08cfb83f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -269,35 +269,6 @@ fsl,heap-id = <0>; }; - gpu_subsys: bus@53100000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x53100000 0x0 0x53100000 0x40000>; - - gpu_3d0: gpu@53100000 { - compatible = "fsl,imx8-gpu"; - reg = <0x53100000 0x40000>; - interrupts = ; - clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; - clock-names = "core", "shader"; - assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; - assigned-clock-rates = <700000000>, <850000000>; - power-domains = <&pd IMX_SC_R_GPU_0_PID0>; - status = "disabled"; - }; - - imx8_gpu_ss: imx8_gpu_ss { - compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; - cores = <&gpu_3d0>; - reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; - reg-names = "phys_baseaddr", "contiguous_mem"; - status = "disabled"; - }; - }; - rpmsg: rpmsg{ compatible = "fsl,imx8qxp-rpmsg"; /* up to now, the following channels are used in imx rpmsg @@ -315,6 +286,7 @@ /* sorted in register address */ #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-dc.dtsi" #include "imx8-ss-lvds.dtsi" -- cgit v1.2.3