From 9b260c850164ee5c907b6c90a86d54e1b4ff29fe Mon Sep 17 00:00:00 2001 From: Stoica Cosmin-Stefan Date: Mon, 8 Jun 2015 18:55:18 +0300 Subject: arm64: Prepare S32V234 dtsi for clock support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update device tree with nodes needed by the clock driver, including clock generation module (MC_CGM), mode entry module (MC_ME) and system reset controller (SRC). Signed-off-by: Stoica Cosmin-Stefan Signed-off-by: Dragoș Papavă Signed-off-by: Stefan-Gabriel Mirea --- arch/arm64/boot/dts/freescale/s32v234.dtsi | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/s32v234.dtsi') diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 355009ada915..a57dcc859875 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -20,6 +20,22 @@ serial1 = &uart1; }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + fxosc { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -113,6 +129,17 @@ reg = <0x0 0x40000000 0x0 0x7d000>; ranges; + clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; + }; + + mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; + }; + uart0: serial@40053000 { compatible = "fsl,s32v234-linflexuart"; reg = <0x0 0x40053000 0x0 0x1000>; @@ -125,6 +152,12 @@ reg = <0x0 0x4006C000 0x0 0x1794>; status = "disabled"; }; + + src: src@4007c000 { + compatible = "fsl,s32v234-src"; + reg = <0x0 0x4007C000 0x0 0x1000>; + #reset-cells = <1>; + }; }; aips1: aips-bus@40080000 { -- cgit v1.2.3