From 128d8860d36cae0fde174535d9ba965898403021 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 14 Feb 2022 13:31:32 +0100 Subject: arm64: dts: imx8mm-verdin: Update IOMUX configuration Update IOMUX configuration as required by the hardware design team. Signed-off-by: Andrejs Cainikovs --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 302 +++++++++++------------ 1 file changed, 151 insertions(+), 151 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 5c2c8cca65d1..b84182754533 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -818,38 +818,38 @@ pinctrl_can1_int: can1intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 /* CAN_1_SPI_INT#_1.8V */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146 /* CAN_1_SPI_INT#_1.8V */ >; }; pinctrl_can2_int: can2intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 /* CAN_2_SPI_INT#_1.8V */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106 /* CAN_2_SPI_INT#_1.8V */ >; }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */ + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106 /* SODIMM 256 */ >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6 /* SODIMM 202 */ >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 /* CAN_SPI_SCK_1.8V */ - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 /* CAN_SPI_MOSI_1.8V */ - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 /* CAN_SPI_MISO_1.8V */ - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 /* CAN_1_SPI_CS_1.8V# */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 /* CAN_2_SPI_CS#_1.8V */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6 /* CAN_SPI_SCK_1.8V */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6 /* CAN_SPI_MOSI_1.8V */ + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6 /* CAN_SPI_MISO_1.8V */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6 /* CAN_1_SPI_CS_1.8V# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146 /* CAN_2_SPI_CS#_1.8V */ >; }; @@ -869,7 +869,7 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 >; }; @@ -889,195 +889,195 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ - MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ - MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106 /* SODIMM 62 */ >; }; pinctrl_gpio1: gpio1grp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106 /* SODIMM 206 */ >; }; pinctrl_gpio2: gpio2grp { fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4 /* SODIMM 208 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106 /* SODIMM 208 */ >; }; pinctrl_gpio3: gpio3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106 /* SODIMM 210 */ >; }; pinctrl_gpio4: gpio4grp { fsl,pins = < - MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106 /* SODIMM 212 */ >; }; pinctrl_gpio5: gpio5grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106 /* SODIMM 216 */ >; }; pinctrl_gpio6: gpio6grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106 /* SODIMM 218 */ >; }; pinctrl_gpio7: gpio7grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106 /* SODIMM 220 */ >; }; pinctrl_gpio8: gpio8grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106 /* SODIMM 222 */ >; }; /* Verdin GPIO_9_DSI (pulled-up as active-low) */ pinctrl_gpio_9_dsi: gpio9dsigrp { fsl,pins = < - MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4 /* SODIMM 17 */ + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146 /* SODIMM 17 */ >; }; /* Verdin GPIO_10_DSI */ pinctrl_gpio_10_dsi: gpio10dsigrp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x106 /* SODIMM 21 */ >; }; pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = < - MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ - MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ - MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ - MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ - MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106 /* SODIMM 120 */ >; }; pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106 /* SODIMM 91 */ >; }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146 /* SODIMM 187 */ >; }; pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4 /* SODIMM 252 */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146 /* SODIMM 252 */ >; }; /* On-module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 /* PMIC_I2C_SCL */ - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 /* PMIC_I2C_SDA */ + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146 /* PMIC_I2C_SDA */ >; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6 /* PMIC_I2C_SCL */ - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6 /* PMIC_I2C_SDA */ + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146 /* PMIC_I2C_SDA */ >; }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146 /* SODIMM 53 */ >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6 /* SODIMM 55 */ - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6 /* SODIMM 53 */ + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146 /* SODIMM 53 */ >; }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146 /* SODIMM 93 */ >; }; pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6 /* SODIMM 95 */ - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6 /* SODIMM 93 */ + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146 /* SODIMM 93 */ >; }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146 /* SODIMM 12 */ >; }; pinctrl_i2c4_gpio: i2c4gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6 /* SODIMM 14 */ - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6 /* SODIMM 12 */ + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146 /* SODIMM 12 */ >; }; /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6 /* SODIMM 42 */ >; }; /* Verdin I2S_2_D_OUT shared with SAI5 */ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184 /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6 /* SODIMM 46 */ >; }; @@ -1090,7 +1090,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /* PMIC_INT# */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 /* PMIC_INT# */ >; }; @@ -1116,93 +1116,93 @@ /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184 /* SODIMM 19 */ + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6 /* SODIMM 19 */ >; }; pinctrl_reg_eth: regethgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 /* PMIC_EN_ETH */ + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146 /* PMIC_EN_ETH */ >; }; pinctrl_reg_usb1_en: regusb1engrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106 /* SODIMM 155 */ >; }; pinctrl_reg_usb2_en: regusb2engrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106 /* SODIMM 185 */ >; }; pinctrl_sai2: sai2grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ - MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6 /* SODIMM 32 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6 /* SODIMM 34 */ >; }; pinctrl_sai5: sai5grp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ - MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ - MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ - MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6 /* SODIMM 46 */ >; }; /* control signal for optional ATTPM20P or SE050 */ pinctrl_pmic_tpm_ena: pmictpmenagrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4 /* PMIC_TPM_ENA */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106 /* PMIC_TPM_ENA */ >; }; pinctrl_tsp: tspgrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* SODIMM 148 */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* SODIMM 152 */ - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140 /* SODIMM 154 */ - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 /* SODIMM 179 */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 /* SODIMM 150 */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6 /* SODIMM 148 */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6 /* SODIMM 152 */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6 /* SODIMM 154 */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146 /* SODIMM 179 */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6 /* SODIMM 150 */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ - MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x146 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x146 /* SODIMM 147 */ >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1c4 /* SODIMM 129 */ - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1c4 /* SODIMM 131 */ - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x146 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x146 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146 /* SODIMM 135 */ >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146 /* SODIMM 143 */ >; }; pinctrl_uart4: uart4grp { fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146 /* SODIMM 153 */ >; }; @@ -1259,112 +1259,112 @@ pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6 /* SODIMM 84 */ >; }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6 /* SODIMM 76 */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; /* On-module Wi-Fi/BT or type specific SDHC interface (e.g. on X52 extension slot of Verdin Development Board */ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 /* PMIC_WDI */ + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 /* PMIC_WDI */ >; }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146 /* WIFI_W_WKUP_HOST */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46 /* WIFI_WKUP_WLAN */ >; }; pinctrl_wifi_i2s: bti2sgrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 /* WIFI_TX_BCLK */ - MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 /* WIFI_TX_DATA0 */ - MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 /* WIFI_TX_SYNC */ - MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 /* WIFI_RX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6 /* WIFI_TX_BCLK */ + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6 /* WIFI_TX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6 /* WIFI_TX_SYNC */ + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6 /* WIFI_RX_DATA0 */ >; }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6 /* PMIC_EN_WIFI */ >; }; }; -- cgit v1.2.3