From d78d416ca78b10c7aede49f8d0c89ecc1d1d460b Mon Sep 17 00:00:00 2001 From: Zhou Peng Date: Tue, 27 Aug 2019 17:16:47 +0800 Subject: arm64: dts: imx845: add vpu decoder enable 845 g1/g2 in device tree Signed-off-by: Zhou Peng --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 8 ++++++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 30 ++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) mode change 100644 => 100755 arch/arm64/boot/dts/freescale/imx8mm-evk.dts mode change 100644 => 100755 arch/arm64/boot/dts/freescale/imx8mm.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts old mode 100644 new mode 100755 index c91367b3099b..3ebb961821d8 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -639,3 +639,11 @@ }; }; }; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi old mode 100644 new mode 100755 index 4c37907db197..c0faf0f3be47 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1179,4 +1179,34 @@ &mu 3 1>; status = "disabled"; }; + + vpu_g1: vpu_g1@38300000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38300000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g1_pd>; + status = "disabled"; + }; + + vpu_g2: vpu_g2@38310000 { + compatible = "nxp,imx8mm-hantro"; + reg = <0x0 0x38310000 0x0 0x100000>; + reg-names = "regs_hantro"; + interrupts = ; + interrupt-names = "irq_hantro"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>, <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_g2_pd>; + status = "disabled"; + }; }; -- cgit v1.2.3