From 60792ad349f3c6dc5735aafefe5dc9121c79e320 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Fri, 18 Dec 2015 10:35:54 +0000 Subject: arm64: kernel: enforce pmuserenr_el0 initialization and restore The pmuserenr_el0 register value is architecturally UNKNOWN on reset. Current kernel code resets that register value iff the core pmu device is correctly probed in the kernel. On platforms with missing DT pmu nodes (or disabled perf events in the kernel), the pmu is not probed, therefore the pmuserenr_el0 register is not reset in the kernel, which means that its value retains the reset value that is architecturally UNKNOWN (system may run with eg pmuserenr_el0 == 0x1, which means that PMU counters access is available at EL0, which must be disallowed). This patch adds code that resets pmuserenr_el0 on cold boot and restores it on core resume from shutdown, so that the pmuserenr_el0 setup is always enforced in the kernel. Cc: Cc: Mark Rutland Signed-off-by: Lorenzo Pieralisi Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm64/kernel/perf_event.c') diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index d880e9cf058b..f0356a8f6110 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -705,9 +705,6 @@ static void armv8pmu_reset(void *info) /* Initialize & Reset PMNC: C and P bits. */ armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C); - - /* Disable access from userspace. */ - asm volatile("msr pmuserenr_el0, %0" :: "r" (0)); } static int armv8_pmuv3_map_event(struct perf_event *event) -- cgit v1.2.3