From 7ae82f64e9648cca0e3c9f59a678b80138d251e1 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 4 Dec 2019 19:03:59 -0600 Subject: LF-363 arm64: kernel: TKT340553 Errata workaround update for i.MX8QM As per latest i.MX8QM SOC Errata, TKT340553 workaround needs to be updated to unconditionally downgrade TLB operations and instruction cache maintenance. Signed-off-by: Nitin Garg Signed-off-by: Anson Huang Acked-by: Peng Fan --- arch/arm64/kvm/hyp/tlb.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm64/kvm') diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index eb0efc5557f3..6a109156681c 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -16,6 +16,8 @@ struct tlb_inv_context { u64 sctlr; }; +extern bool TKT340553_SW_WORKAROUND; + static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm, struct tlb_inv_context *cxt) { @@ -126,8 +128,12 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ - ipa >>= 12; - __tlbi(ipas2e1is, ipa); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalls12e1is); + } else { + ipa >>= 12; + __tlbi(ipas2e1is, ipa); + } /* * We have to ensure completion of the invalidation at Stage-2, -- cgit v1.2.3