From dab218c3c46644215f5709e03729bbe9ba3b5823 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Thu, 2 Aug 2018 13:47:10 +0800 Subject: MLK-19114-1 arm64: fsl-imx8qm.dtsi: Add aux prg for dpr1/3_channel2 With the updated i.MX8QM silicon, prg1/10 may be shared bewteen dpr1/3_channel1 and dpr1/3_channel2 respectively with appropriate mux configurations in SCU firmware. If prg1/10 are attached to dpr1/3_channel2, then they act as the auxiliary prg to process chroma pixels for SC_R_DC_0/1_BLIT1. Otherwise, they act as the primary prg to process RGB pixels for SC_R_DC_0/1_BLIT0. Let's reflect this update in the device tree file. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index a6f609057b13..9e9fdc388ed9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1633,7 +1633,7 @@ compatible = "fsl,imx8qm-dpr-channel"; reg = <0x0 0x560e0000 0x0 0x10000>; fsl,sc-resource = ; - fsl,prgs = <&prg2>; + fsl,prgs = <&prg2>, <&prg1>; clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>, <&clk IMX8QM_DC0_DPR0_B_CLK>, <&clk IMX8QM_DC0_RTRAM0_CLK>; @@ -2097,7 +2097,7 @@ compatible = "fsl,imx8qm-dpr-channel"; reg = <0x0 0x570e0000 0x0 0x10000>; fsl,sc-resource = ; - fsl,prgs = <&prg11>; + fsl,prgs = <&prg11>, <&prg10>; clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>, <&clk IMX8QM_DC1_DPR0_B_CLK>, <&clk IMX8QM_DC1_RTRAM0_CLK>; -- cgit v1.2.3