From 72cd7447e72a13ce72d760b42ec295430f77300a Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 17 Apr 2013 12:05:58 +0200 Subject: ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/ pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 151259003086..ca1717135820 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -177,7 +177,8 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; -static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; @@ -369,8 +370,8 @@ int __init mx6q_clocks_init(void) clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); -- cgit v1.2.3 From 0e574461c4c915a065dd75c894edb653ce99be9c Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 22 Apr 2013 08:00:34 +0200 Subject: ARM i.MX6: correct MLB clock configuration According to the i.MX6 Dual/Quad technical reference manual (Figure 18-2. Clock Tree - Part 1) the MLB clock is directly feed by the AXI_CLK_ROOT. This is called 'axi' in our code. Note that the clock of the MLB IP block on the i.MX6 is completely independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible for feeding the MLB IP block with a clock. Instead, it's used internally by the MLB module to sync the bus clock in case the MLB 6-pin interface is enabled: MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN: 1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case. I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed for clocking the MLB module itself. Signed-off-by: Dirk Behme CC: Jiada Wang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index ca1717135820..f2e1c62cf3ce 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -499,7 +499,7 @@ int __init mx6q_clocks_init(void) clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); - clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18); + clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); -- cgit v1.2.3 From 087bb28329f3ccda4e50cb4cf297542d7e773e20 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 16 Apr 2013 22:11:19 +0800 Subject: ARM: imx: replicate the diagnostic register of boot cpu into secondary cores The diagnostic register holds the errata bits. Mostly bootloader does not bring up secondary cores, so that when errata bits are set in bootloader, they are set only for boot cpu. But on a SMP configuration, it should be equally done on every single core. Set up the diagnostic register for secondary cores by replicating the register from boot cpu. Signed-off-by: Shawn Guo Acked-by: Dirk Behme --- arch/arm/mach-imx/headsmp.S | 12 ++++++++++++ arch/arm/mach-imx/platsmp.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 67b9c48dcafe..627f16f0e9d1 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -18,8 +18,20 @@ .section ".text.head", "ax" #ifdef CONFIG_SMP +diag_reg_offset: + .word g_diag_reg - . + + .macro set_diag_reg + adr r0, diag_reg_offset + ldr r1, [r0] + add r1, r1, r0 @ r1 = physical &g_diag_reg + ldr r0, [r1] + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register + .endm + ENTRY(v7_secondary_startup) bl v7_invalidate_l1 + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) #endif diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 4a69305db65e..c6e1ab544882 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -21,6 +22,7 @@ #define SCU_STANDBY_ENABLE (1 << 5) +u32 g_diag_reg; static void __iomem *scu_base; static struct map_desc scu_io_desc __initdata = { @@ -80,6 +82,18 @@ void imx_smp_prepare(void) static void __init imx_smp_prepare_cpus(unsigned int max_cpus) { imx_smp_prepare(); + + /* + * The diagnostic register holds the errata bits. Mostly bootloader + * does not bring up secondary cores, so that when errata bits are set + * in bootloader, they are set only for boot cpu. But on a SMP + * configuration, it should be equally done on every single core. + * Read the register from boot cpu here, and will replicate it into + * secondary cores when booting them. + */ + asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); + __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg)); + outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1)); } struct smp_operations imx_smp_ops __initdata = { -- cgit v1.2.3 From de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 3 May 2013 10:55:46 +0800 Subject: ARM: imx: fix typo in gpu3d_shader_sels There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m. Fix the typo in gpu3d_shader_sels. Signed-off-by: Shawn Guo Acked-by: Dirk Behme --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index f2e1c62cf3ce..dda9a2bd3acb 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -186,7 +186,7 @@ static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; -static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; +static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; -- cgit v1.2.3 From d34c671debe3d327424a9951a5c3a81065d0474d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 18 Apr 2013 22:44:29 +0200 Subject: ARM: sunxi: Fix Mini X-plus device tree build Commit b00adbe0 ("ARM: sunxi: Rename uart nodes to serial") changed the node names in the DTSI, changes that were not accordingly made to the Mini X-Plus device tree. This breakage slipped through because it was not properly declared in the Makefile. Fix both issues. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 4 +++- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ecf..f0895c581a89 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -177,7 +177,9 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \ +dtb-$(CONFIG_ARCH_SUNXI) += \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ sun5i-a13-olinuxino.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 4a7c35d6726a..078ed7f618d7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -22,8 +22,8 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc { - uart0: uart@01c28000 { + soc@01c20000 { + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; -- cgit v1.2.3 From be3cd268d1d1837aaed937c2fc85b3d39d2f1b50 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Apr 2013 23:26:18 +0200 Subject: ARM: mvebu: do not duplicate the mpic alias The mpic alias is already defined in the common armada-370-xp.dtsi, so there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi level. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 2 +- arch/arm/boot/dts/armada-xp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b2c1b5af9749..0c9130b6fb80 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -43,7 +43,7 @@ wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bacab11c10dc..5b902f9a3af2 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -31,7 +31,7 @@ wt-override; }; - mpic: interrupt-controller@20000 { + interrupt-controller@20000 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; -- cgit v1.2.3 From 99e11334dcb846f9b76fb808196c7f47aa83abb3 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Sun, 21 Apr 2013 17:14:00 +0100 Subject: Kirkwood: Enable PCIe port 1 on QNAP TS-11x/TS-21x Enable KW_PCIE1 on QNAP TS-11x/TS-21x devices as newer revisions (rev 1.3) have a USB 3.0 chip from Etron on PCIe port 1. Thanks to Marek Vasut for identifying this issue! Cc: # v2.6.36.x Signed-off-by: Martin Michlmayr Tested-by: Marek Vasut Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/ts219-setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 283abff90228..e1267d6b468f 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -124,7 +124,7 @@ static void __init qnap_ts219_init(void) static int __init ts219_pci_init(void) { if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); + kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); return 0; } -- cgit v1.2.3 From 7c14068f5a08d57d5ea98ef3668218e654617095 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Fri, 10 May 2013 22:12:27 +0200 Subject: ARM: plat-orion: add missing ehci include to common.h Removing orion ehci include from board files will raise a compiler error because plat/common.h is using an enum provided by orion ehci but not including the include itself. This just adds the missing include. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/plat-orion/include/plat/common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index e06fc5fefa14..d9a24f605a2b 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -10,6 +10,7 @@ #ifndef __PLAT_COMMON_H #include +#include struct dsa_platform_data; struct mv_sata_platform_data; -- cgit v1.2.3 From 00ed4a0bd964555fe9276f2299564c384d50ae7d Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 13 May 2013 12:22:53 -0300 Subject: ARM: mvebu: Add a ranges entry to translate devbus childs With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index f14d36c46159..46b785064dd8 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,6 +27,9 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 + 0xf0000000 0 0xf0000000 0x8000000>; + internal-regs { serial@12000 { clock-frequency = <250000000>; -- cgit v1.2.3 From 6d31727a0b6fe7206725c93508e6d2065f16ff03 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 13 May 2013 19:32:14 +0000 Subject: ARM: Orion: Remove redundant init_dma_coherent_pool_size() The patch: 387870f mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls makes these calls on Kirkwood and Orion5x redundant. The drivers are not making atomic requests for coherent memory and hence the default pool size is now sufficient. Jason Cooper added mach-mvebu/ hunk, and corrected minor typos in commit message. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/common.c | 6 ------ arch/arm/mach-mvebu/armada-370-xp.c | 7 ------- arch/arm/mach-orion5x/common.c | 7 ------- 3 files changed, 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index c2cae69e6d2b..f38922897563 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -528,12 +528,6 @@ void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); - /* - * Some Kirkwood devices allocate their coherent buffers from atomic - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); mvebu_mbus_init("marvell,kirkwood-mbus", BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 42a4cb3087e2..1c48890bb72b 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -53,13 +53,6 @@ void __init armada_370_xp_init_early(void) { char *mbus_soc_name; - /* - * Some Armada 370/XP devices allocate their coherent buffers - * from atomic context. Increase size of atomic coherent pool - * to make sure such the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); - /* * This initialization will be replaced by a DT-based * initialization once the mvebu-mbus driver gains DT support. diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index b97fd672e89d..f8a6db9239bf 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -199,13 +199,6 @@ void __init orion5x_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); - /* - * Some Orion5x devices allocate their coherent buffers from atomic - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); - /* Initialize the MBUS driver */ orion5x_pcie_id(&dev, &rev); if (dev == MV88F5281_DEV_ID) -- cgit v1.2.3 From 3210c05327e2b44b3bf96bab550d72cdb18b64e4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 8 May 2013 14:29:01 +0100 Subject: ARM: ux500: Remove duplicated assignment of ab8500_platdata Since: "05ec260 mfd: db8500-prcmu: update resource passing", the AB8500's platform data 'ab8500_platdata' is passed directly as an attribute to 'db8500_prcmu_pdata', so there's no requirement to assign it a second time. In fact, it's only due to an ordering issue that the entire 'db8500_prcmu_pdata' data structure isn't completely over-written by the assignment in u8500_init_devices(). Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500.c | 6 +++--- arch/arm/mach-ux500/cpu-db8500.c | 4 +--- arch/arm/mach-ux500/setup.h | 2 +- 3 files changed, 5 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 3cd555ac6d0a..78389de94dde 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -623,7 +623,7 @@ static void __init mop500_init_machine(void) sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL; mop500_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; @@ -660,7 +660,7 @@ static void __init snowball_init_machine(void) sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO; snowball_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) snowball_platform_devs[i]->dev.parent = parent; @@ -698,7 +698,7 @@ static void __init hrefv60_init_machine(void) sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO; hrefv60_pinmaps_init(); - parent = u8500_init_devices(&ab8500_platdata); + parent = u8500_init_devices(); for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index e90b5ab23b6d..8894327283e1 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -206,7 +206,7 @@ static struct device * __init db8500_soc_device_init(void) /* * This function is called from the board init */ -struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) +struct device * __init u8500_init_devices(void) { struct device *parent; int i; @@ -220,8 +220,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) for (i = 0; i < ARRAY_SIZE(platform_devs); i++) platform_devs[i]->dev.parent = parent; - db8500_prcmu_device.dev.platform_data = ab8500; - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); return parent; diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index bddce2b49372..cad3ca86c540 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -18,7 +18,7 @@ void __init ux500_map_io(void); extern void __init u8500_map_io(void); -extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500); +extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); extern void __init ux500_init_late(void); -- cgit v1.2.3 From ea63a11027103372f56bd2d9ee3c525be6edc9c1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 8 May 2013 14:29:05 +0100 Subject: ARM: ux500: Fix incorrect DEBUG UART virtual addresses A recent move to rid header files which were hindering multiplatform support forced address allocations out of the headers and into the files which were using them. We also lost some useful macros such as IO_ADDRESS(), so physical -> virtual addressing has been carried out manually in this case. Unfortunately the incorrect value was converted. This patch rectifies the error and ensures earlyprintk works again. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/include/debug/ux500.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S index 2848857f5b62..fbd24beeb1fa 100644 --- a/arch/arm/include/debug/ux500.S +++ b/arch/arm/include/debug/ux500.S @@ -24,9 +24,9 @@ #define U8500_UART0_PHYS_BASE (0x80120000) #define U8500_UART1_PHYS_BASE (0x80121000) #define U8500_UART2_PHYS_BASE (0x80007000) -#define U8500_UART0_VIRT_BASE (0xa8120000) -#define U8500_UART1_VIRT_BASE (0xa8121000) -#define U8500_UART2_VIRT_BASE (0xa8007000) +#define U8500_UART0_VIRT_BASE (0xf8120000) +#define U8500_UART1_VIRT_BASE (0xf8121000) +#define U8500_UART2_VIRT_BASE (0xf8007000) #define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE #define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE #endif -- cgit v1.2.3 From 7d2b64f9832d7cb971141703219b3dc495bb9332 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 8 May 2013 14:29:06 +0100 Subject: ARM: ux500: Provide device enumeration number suffix for SMSC911x First Ethernet device has a ".0" appended onto the device name. Since on a non-DT boot the ethernet will be named "smsc911x.0" and since the clocks are not converted to device tree these names need to be matched when providing the name from auxdata. Signed-off-by: Lee Jones [edited commit message] Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu-db8500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 8894327283e1..46cca52890bc 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -276,7 +276,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), - OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL), + OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, "pinctrl-db8500", NULL), -- cgit v1.2.3 From 9349d00fc3ff2b110dc07d9f5d06abfeac300c19 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 7 May 2013 22:06:57 +0200 Subject: ARM: at91/trivial: fix model name for SAM9X25-EK Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre Cc: stable # 3.8+ --- arch/arm/boot/dts/at91sam9x25ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 3b40d11d65e7..315250b4995e 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -11,7 +11,7 @@ /include/ "at91sam9x5ek.dtsi" / { - model = "Atmel AT91SAM9G25-EK"; + model = "Atmel AT91SAM9X25-EK"; compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; ahb { -- cgit v1.2.3 From 5ade7e4214b43e9b934202d892e3d7c131617908 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 14 May 2013 15:14:49 +0200 Subject: ARM: at91/trivial: typo in GEM compatible string Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 2e643ea51cce..5fce96b1cee4 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -156,7 +156,7 @@ }; macb0: ethernet@f0028000 { - compatible = "cnds,pc302-gem", "cdns,gem"; + compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; interrupts = <34 4 3>; pinctrl-names = "default"; -- cgit v1.2.3 From 3f81127293284da449942a0144b9747c5db1e523 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Wed, 24 Apr 2013 15:56:48 +0200 Subject: ARM: at91: dts: request only spi cs-gpios used on sama5d3x cpu module Instead of requesting all available spi cs-gpios, request only the ones used on the board, in our case on the cpu module. Signed-off-by: Ludovic Desroches Acked-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 10 ---------- arch/arm/boot/dts/sama5d3xcm.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5fce96b1cee4..5000e0d42849 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -75,11 +75,6 @@ compatible = "atmel,at91sam9x5-spi"; reg = <0xf0004000 0x100>; interrupts = <24 4 3>; - cs-gpios = <&pioD 13 0 - &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ - &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ - &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ - >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -203,11 +198,6 @@ compatible = "atmel,at91sam9x5-spi"; reg = <0xf8008000 0x100>; interrupts = <25 4 3>; - cs-gpios = <&pioC 25 0 - &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ - &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ - &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ - >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 1f8ed404626c..b336e7787cb3 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -32,6 +32,10 @@ ahb { apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + macb0: ethernet@f0028000 { phy-mode = "rgmii"; }; -- cgit v1.2.3 From 19a280a61b520febab0f2fde94f4bd50250377b2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 12 May 2013 15:06:51 +0200 Subject: ARM: sunxi: select ARCH_REQUIRE_GPIOLIB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CONFIG_ARCH_SUNXI currently doesn't enable a gpiolib, which causes build problems when building a kernel with only the sunxi platform enabled. Select ARCH_REQUIRE_GPIOLIB to solve this. Signed-off-by: Maxime Ripard Tested-by: Emilio López --- arch/arm/mach-sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d259c782d742..5b045e302b43 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,5 +1,6 @@ config ARCH_SUNXI bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK -- cgit v1.2.3 From b7a8ca5173ef9aa55fa039d7c216426ff0b25a12 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 15 May 2013 12:12:33 +0200 Subject: ARM: at91: rm9200 fix time support since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488 Author: Shawn Guo Date: Sat Jan 12 11:50:05 2013 +0000 ARM: use clockevents_config_and_register() where possible The timer is wrongly configured and result in a nice crash so revert it on rm9200 timer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: stable # 3.8+ Cc: Shawn Guo Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/at91rm9200_time.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 2acdff4c1dfe..180b3024bec3 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) static struct clock_event_device clkevt = { .name = "at91_tick", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, .rating = 150, .set_next_event = clkevt32k_next_event, .set_mode = clkevt32k_mode, @@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void) at91_st_write(AT91_ST_RTMR, 1); /* Setup timer clockevent, with minimum of two ticks (important!!) */ + clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; clkevt.cpumask = cpumask_of(0); - clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, - 2, AT91_ST_ALMV); + clockevents_register_device(&clkevt); /* register clocksource */ clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); -- cgit v1.2.3 From 74ba4ec7a2036f9dbe5fcc85c7c737222005507f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Wed, 15 May 2013 09:36:41 -0300 Subject: ARM: ux500: select REGULATOR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MACH_MOP500 selects REGULATOR_FIXED_VOLTAGE but not REGULATOR. This patch makes it select the latter too. Seen as: warning: (MACH_DOVE_DT && ARCH_KIRKWOOD_DT && MACH_AMS_DELTA && MACH_MOP500 && TPS6105X) selects REGULATOR_FIXED_VOLTAGE which has unmet direct dependencies (REGULATOR) Signed-off-by: Emilio López Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 6a4387e39df8..b19b07204aaf 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -51,6 +51,7 @@ config MACH_MOP500 bool "U8500 Development platform, MOP500 versions" select I2C select I2C_NOMADIK + select REGULATOR select REGULATOR_FIXED_VOLTAGE select SOC_BUS select UX500_SOC_DB8500 -- cgit v1.2.3 From 98f541c6e390d48643047e0924da8ccc10bb1598 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Wed, 1 May 2013 12:13:54 -0400 Subject: USB: remove remaining instances of USB_SUSPEND Commit 84ebc10294a3d7be4c66f51070b7aedbaa24de9b (USB: remove CONFIG_USB_SUSPEND option) failed to remove all of the usages of USB_SUSPEND throughout the kernel. This patch (as1677) removes the remaining instances of that symbol. Signed-off-by: Alan Stern Signed-off-by: Greg Kroah-Hartman --- arch/arm/configs/omap1_defconfig | 1 - arch/arm/configs/omap2plus_defconfig | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 7e0ebb64a7f9..9940f7b4e438 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -199,7 +199,6 @@ CONFIG_USB_PHY=y CONFIG_USB_DEBUG=y CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c1ef64bc5abd..435d69b83e32 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -204,7 +204,6 @@ CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_MON=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y -- cgit v1.2.3 From 304e71e0ad4125c29a0731491b75c3b83530d616 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 14 May 2013 20:28:15 -0700 Subject: ARM: dts: Fix musb interrupt for device tree booting Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards) added support for MUSB on omap3 for device tree, but added the interrupts the wrong way probably as they were copied from the omap4.dtsi file. On omap3 we have TI specific interrupt controller, not GIC. Fix this by specifying the interrupt following the TI INTC binding. Without this fix MUSB won't work as it is trying to use irq0 instead of irq92. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 82a404da1c0d..99ba6e14ebf3 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -516,7 +516,7 @@ usb_otg_hs: usb_otg_hs@480ab000 { compatible = "ti,omap3-musb"; reg = <0x480ab000 0x1000>; - interrupts = <0 92 0x4>, <0 93 0x4>; + interrupts = <92>, <93>; interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; multipoint = <1>; -- cgit v1.2.3 From 0f497039276fa2ca2ca324236848bb15c8c775dc Mon Sep 17 00:00:00 2001 From: jean-philippe francois Date: Thu, 16 May 2013 11:25:07 -0700 Subject: ARM: OMAP: fix __init section mismatch for _enable_preprogram _enable_preprogram is marked as __init, but is called from _enable which is not. Without this patch, the board oopses after init. Tested on custom hardware and on beagle board xM. Otherwise we can get: Unable to handle kernel paging request at virtual address 000b0012 pgd = cf968000 *pgd=8fb06831, *pte=00000000, *ppte=00000000 PREEMPT ARM Modules linked in: CPU: 0 Not tainted (3.9.0 #2) PC is at _enable_preprogram+0x1c/0x24 LR is at omap_hwmod_enable+0x34/0x60 psr: 80000093 sp : cf95de08 ip : 00002de5 fp : bec33d4c r10: 00000000 r9 : 00000002 r8 : b6dd2c78 r7 : 00000004 r6 : 00000000 r5 : a0000013 r4 : cf95c000 r3 : 00000000 r2 : b6dd2c7c r1 : 00000000 r0 : 000b0012 Flags: Nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c5387d Table: 8f968019 DAC: 00000015 Process otpcmd (pid: 607, stack limit = 0xcf95c230) Stack: (0xcf95de08 to 0xcf95e000) de00: 00000001 cf91f840 00000000 c001d6fc 00000002 cf91f840 de20: cf8f7e10 c001de54 cf8f7e10 c001de78 c001de68 c01d5e80 00000000 cf8f7e10 de40: cf8f7e10 c01d5f28 cf8f7e10 c0530d30 00000000 c01d6f28 00000000 c0088664 de60: b6ea1000 cfb05284 cf95c000 00000001 cf95c000 60000013 00000001 cf95dee4 de80: cf870050 c01d7308 cf870010 cf870050 00000001 c0278b14 c0526f28 00000000 dea0: cf870050 ffff8e18 00000001 cf95dee4 00000000 c0274f7c cf870050 00000001 dec0: cf95dee4 cf1d8484 000000e0 c0276464 00000008 cf9c0000 00000007 c0276980 dee0: cf9c0000 00000064 00000008 cf1d8404 cf1d8400 c01cc05c 0000270a cf1d8504 df00: 00000023 cf1d8484 00000007 c01cc670 00000bdd 00000001 00000000 cf449e60 df20: cf1dde70 cf1d8400 bec33d18 cf1d8504 c0246f00 00000003 cf95c000 00000000 df40: bec33d4c c01cd078 00000003 cf1d8504 00000081 c01cbcb8 bec33d18 00000003 df60: bec33d18 c00a9034 00002000 c00a9c68 cf92fe00 00000003 c0246f00 cf92fe00 df80: 00000000 c00a9cb0 00000003 00000000 00008e70 00000000 b6f17000 00000036 dfa0: c000e484 c000e300 00008e70 00000000 00000003 c0246f00 bec33d18 bec33d18 dfc0: 00008e70 00000000 b6f17000 00000036 00000000 00000000 b6f6d000 bec33d4c dfe0: b6ea1bd0 bec33d0c 00008c9c b6ea1bdc 60000010 00000003 00000000 00000000 (_omap_device_enable_hwmods+0x20/0x34) (omap_device_enable+0x3c/0x50) (_od_runtime_resume+0x10/0x1c) (__rpm_callback+0x54/0x98) (rpm_callback+0x64/0x7c) (rpm_resume+0x434/0x554) (__pm_runtime_resume+0x48/0x74) (omap_i2c_xfer+0x28/0xe8) (__i2c_transfer+0x3c/0x78) (i2c_transfer+0x6c/0xc0) (i2c_master_send+0x38/0x48) (sha204p_send_command+0x60/0x9c) (sha204c_send_and_receive+0x5c/0x1e0) (sha204m_read+0x94/0xa0) (otp_do_read+0x50/0xa4) (vfs_ioctl+0x24/0x40) (do_vfs_ioctl+0x1b0/0x1c0) (sys_ioctl+0x38/0x54) (ret_fast_syscall+0x0/0x30) Code: e1a08002 ea000009 e598003c e592c05c (e7904003) Cc: stable@vger.kernel.org Signed-off-by: Jean-Philippe Fran=C3=A7ois Acked-by: Kevin Hilman [tony@atomide.com: updated description with oops] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d25a95fe9921..e3289888adfa 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2065,7 +2065,7 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh) * do so is present in the hwmod data, then call it and pass along the * return value; otherwise, return 0. */ -static int __init _enable_preprogram(struct omap_hwmod *oh) +static int _enable_preprogram(struct omap_hwmod *oh) { if (!oh->class->enable_preprogram) return 0; -- cgit v1.2.3 From a8b09c52a66e801d87704cfebf57958b1991ab86 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Thu, 16 May 2013 11:25:07 -0700 Subject: ARM: OMAP: fix error return code in omap1_system_dma_init() Fix to return -ENOMEM in the d->chan alloc error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/dma.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 68ab858e27b7..a94b3a718d1a 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -345,6 +345,7 @@ static int __init omap1_system_dma_init(void) dev_err(&pdev->dev, "%s: Memory allocation failed for d->chan!\n", __func__); + ret = -ENOMEM; goto exit_release_d; } -- cgit v1.2.3 From a545ec160afea245939290e7f616f68de906a85c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 16 May 2013 11:25:07 -0700 Subject: ARM: OMAP2+: Add missing CONFIG_ARCH_MULTI_V6=y to omap2plus_defconfig omap2plus_defconfig is missing CONFIG_ARCH_MULTI_V6. This results in undefined instruction traps in u-boot (and boot failures) on OMAP2xxx SoCs, which are ARM11-based. Fix by setting CONFIG_ARCH_MULTI_V6. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c1ef64bc5abd..f59090210ec9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -20,6 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX_DEBUG=y -- cgit v1.2.3 From c6c003af0b91bb8722dbf2a8683cd40532e12079 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 17 May 2013 08:09:57 -0300 Subject: ARM: mvebu: Fix ranges entry on XP GP board With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. This patch fixes the ranges property on the Armada XP GP board. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-gp.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 26ad06fc147e..3ee63d128e27 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -39,6 +39,9 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 + 0xf0000000 0 0xf0000000 0x1000000>; + internal-regs { serial@12000 { clock-frequency = <250000000>; -- cgit v1.2.3 From a6d25f4c951b8b28f2eaec6f891ff834622532f2 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 27 Mar 2013 15:34:26 +0530 Subject: ARM: AM33XX: Add missing .clkdm_name to clkdiv32k_ick clock It is required to enable respective clock-domain before enabling any clock/module inside that clock-domain. During common-clock migration, .clkdm_name field got missed for "clkdiv32k_ick" clock, which leaves "clk_24mhz_clkdm" unused; so it will be disabled even if childs of this clock-domain is enabled, which keeps child modules in idle mode. This fixes the kernel crash observed on AM335xEVM-SK platform, where clkdiv32_ick clock is being used as a gpio debounce clock and since clkdiv32k_ick is in idle mode it leads to below crash - Crash Log: ========== [ 2.598347] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa1ac150 [ 2.606434] Internal error: : 1028 [#1] SMP ARM [ 2.611207] Modules linked in: [ 2.614449] CPU: 0 Not tainted (3.8.4-01382-g1f449cd-dirty #4) [ 2.620973] PC is at _set_gpio_debounce+0x60/0x104 [ 2.626025] LR is at clk_enable+0x30/0x3c Cc: stable@vger.kernel.org # v3.9 Signed-off-by: Vaibhav Hiremath Cc: Rajendra Nayak Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/cclock33xx_data.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 6ebc7803bc3e..af3544ce4f02 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -454,9 +454,29 @@ DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, */ DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); -DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0, - AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); +static struct clk clkdiv32k_ick; + +static const char *clkdiv32k_ick_parent_names[] = { + "clkdiv32k_ck", +}; + +static const struct clk_ops clkdiv32k_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap clkdiv32k_ick_hw = { + .hw = { + .clk = &clkdiv32k_ick, + }, + .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "clk_24mhz_clkdm", +}; + +DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); /* "usbotg_fck" is an additional clock and not really a modulemode */ DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, -- cgit v1.2.3 From d7fc0dde96248c0d90e02bc95dc5c003ece84982 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 12 May 2013 15:19:55 +0200 Subject: arch/arm/mach-tegra: don't check resource with devm_ioremap_resource devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: Wolfram Sang Acked-by: Stephen Warren --- arch/arm/mach-tegra/tegra2_emc.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index 9e8bdfa2b369..31e69a019bdd 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -307,11 +307,6 @@ static int tegra_emc_probe(struct platform_device *pdev) } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "missing register base\n"); - return -ENOMEM; - } - emc_regbase = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(emc_regbase)) return PTR_ERR(emc_regbase); -- cgit v1.2.3 From c818b58e63f1d9fe1c070f0e578ef5168de35312 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 12 May 2013 15:19:55 +0200 Subject: arch/arm/plat-samsung: don't check resource with devm_ioremap_resource devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: Wolfram Sang --- arch/arm/plat-samsung/adc.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index ca07cb1b155a..79690f2f6d3f 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -381,11 +381,6 @@ static int s3c_adc_probe(struct platform_device *pdev) } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) { - dev_err(dev, "failed to find registers\n"); - return -ENXIO; - } - adc->regs = devm_ioremap_resource(dev, regs); if (IS_ERR(adc->regs)) return PTR_ERR(adc->regs); -- cgit v1.2.3 From c689cbac25b4fce2f3d7de2e4dd6678caeebdcb8 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 17 May 2013 14:25:03 +0200 Subject: ARM: mvebu: select ARCH_REQUIRE_GPIOLIB for mvebu platform Initially ARCH_REQUIRE_GPIOLIB was part of Thomas Petazzoni series when he introduced the gpiolib support for mvebu: 93a59cf arm: mvebu: use GPIO support now that a driver is available This commit was written to be applied for the ARCH_MVEBU which was located in arch/arm/KConfig and was merged in 3.7. In the same time Rob Herring moved the ARCH_MVEBU block to arch/arm/mach-mvebu/Kconfig with this commit and also merged in 3.7: 387798b ARM: initial multiplatform support Unfortunately the ARCH_REQUIRE_GPIOLIB have been lost during this migration. This was not noticed until the v3.10-rc1, because mvebu as part of ARCH_MULTIPLATFORM was always selected with ARCH_VEXPRESS, and this architect selected ARCH_REQUIRE_GPIOLIB. Since the following commit from Arnd: "883a106 ARM: default machine descriptor for multiplatform", ARCH_VEXPRESS was then no more selected by default with ARCH_MVEBU and it made appeared the lack of ARCH_REQUIRE_GPIOLIB for mvebu. This commit added back the selection of ARCH_REQUIRE_GPIOLIB for ARCH_MVEBU. Signed-off-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index e11acbb0a46d..80a8bcacd9d5 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -15,6 +15,7 @@ config ARCH_MVEBU select MVEBU_CLK_GATING select MVEBU_MBUS select ZONE_DMA if ARM_LPAE + select ARCH_REQUIRE_GPIOLIB if ARCH_MVEBU -- cgit v1.2.3 From 8eed481e6fe2c28c2a579ada0c8ba5cbad45bf2c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 May 2013 17:55:16 +0200 Subject: arm: mvebu: fix the 'ranges' property to handle PCIe Since 82a682676 ('ARM: dts: mvebu: Convert all the mvebu files to use the range property') all the device nodes of Armada 370/XP are under a common 'ranges' property that translates the device register addresses into their absolute address, thanks to the base address of the internal register space. However, beyond just the register areas, there are also PCIe I/O and memory regions, whose addresses should be properly translated. This patch fixes the Armada 370 and XP ranges property to take PCIe into account properly. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 3 ++- arch/arm/boot/dts/armada-370.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 272bbc65fab0..550eb772c30e 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -33,7 +33,8 @@ #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&mpic>; - ranges = <0 0 0xd0000000 0x100000>; + ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; internal-regs { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 0c9130b6fb80..a1a870364dd8 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -29,7 +29,8 @@ }; soc { - ranges = <0 0xd0000000 0x100000>; + ranges = <0 0xd0000000 0x0100000 /* internal registers */ + 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; internal-regs { system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; -- cgit v1.2.3 From 35513171eed4d7245e81d926d311e74f3dca06f3 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 15 May 2013 20:18:37 +0530 Subject: ARM: OMAP2+: hwmod: Fix sidle programming in _enable_sysc()/_idle_sysc() _enable_sysc() and _idle_sysc() handle the midle mode programming correctly and program HWMOD_IDLEMODE_SMART or HWMOD_IDLEMODE_SMART_WKUP respectively for supported IPs (The ones which support hardware controlled midle modes) However the same programming logic is missing when it comes to sidle mode programming. Here they seem to just set HWMOD_IDLEMODE_SMART (Again for the ones which support hardware controlled sidle modes) This problem was hidden due to the fact that a call to _enable_wakeup() in those same functions would overwrite the idlemodes and program them correctly (to HWMOD_IDLEMODE_SMART_WKUP in the supported cases) So fix the sidlemode handling correctly in these functions and handle the _enable_wakeup() for SIDLEMODE supported IPs same as the way its handled for MIDLEMODE supported ones. Tested-by: Vaibhav Bedia Tested-by: Sourav Poddar Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman # OMAP4/Panda Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 42 ++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d25a95fe9921..c28552bfeb8d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1356,13 +1356,26 @@ static void _enable_sysc(struct omap_hwmod *oh) clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { + if (oh->flags & HWMOD_SWSUP_SIDLE) { + idlemode = HWMOD_IDLEMODE_NO; + } else { + if (sf & SYSC_HAS_ENAWAKEUP) + _enable_wakeup(oh, &v); + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + } + + /* + * This is special handling for some IPs like + * 32k sync timer. Force them to idle! + */ clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); if (clkdm_act && !(oh->class->sysc->idlemodes & (SIDLE_SMART | SIDLE_SMART_WKUP))) idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? - HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; + _set_slave_idlemode(oh, idlemode, &v); } @@ -1391,10 +1404,6 @@ static void _enable_sysc(struct omap_hwmod *oh) (sf & SYSC_HAS_CLOCKACTIVITY)) _set_clockactivity(oh, oh->class->sysc->clockact, &v); - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh, &v); - _write_sysconfig(v, oh); /* @@ -1430,13 +1439,16 @@ static void _idle_sysc(struct omap_hwmod *oh) sf = oh->class->sysc->sysc_flags; if (sf & SYSC_HAS_SIDLEMODE) { - /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ - if (oh->flags & HWMOD_SWSUP_SIDLE || - !(oh->class->sysc->idlemodes & - (SIDLE_SMART | SIDLE_SMART_WKUP))) + if (oh->flags & HWMOD_SWSUP_SIDLE) { idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = HWMOD_IDLEMODE_SMART; + } else { + if (sf & SYSC_HAS_ENAWAKEUP) + _enable_wakeup(oh, &v); + if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + } _set_slave_idlemode(oh, idlemode, &v); } @@ -1455,10 +1467,6 @@ static void _idle_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } - /* If slave is in SMARTIDLE, also enable wakeup */ - if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) - _enable_wakeup(oh, &v); - _write_sysconfig(v, oh); } -- cgit v1.2.3 From ca43ea345de96dc214be790b6cebedbdfe110b63 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 15 May 2013 20:18:38 +0530 Subject: ARM: OMAP2+: hwmod: Add a new flag to handle SIDLE in SWSUP only in active Some IPs (like UART) need the sidle mode to be controlled in SW only while they are active. Once they go inactive, they need the IP to be put back in HW control so they are also wakeup capable. The flag HWMOD_SWSUP_SIDLE takes care of IPs which need the sidle mode to be *always* controlled in SWSUP. We now have a need to control IPs sidle mode in SWSUP only while its active. So define a new flag 'HWMOD_SWSUP_SIDLE_ACT' to help the framework know about these new IP requirements. Tested-by: Vaibhav Bedia Tested-by: Sourav Poddar Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman # OMAP4/Panda Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 3 ++- arch/arm/mach-omap2/omap_hwmod.h | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c28552bfeb8d..5739429894b0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1356,7 +1356,8 @@ static void _enable_sysc(struct omap_hwmod *oh) clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { - if (oh->flags & HWMOD_SWSUP_SIDLE) { + if (oh->flags & HWMOD_SWSUP_SIDLE || + oh->flags & HWMOD_SWSUP_SIDLE_ACT) { idlemode = HWMOD_IDLEMODE_NO; } else { if (sf & SYSC_HAS_ENAWAKEUP) diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index fe5962921f07..8498774b5fb1 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -463,6 +463,9 @@ struct omap_hwmod_omap4_prcm { * is kept in force-standby mode. Failing to do so causes PM problems * with musb on OMAP3630 at least. Note that musb has a dedicated register * to control MSTANDBY signal when MIDLEMODE is set to force-standby. + * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module + * out of idle, but rely on smart-idle to the put it back in idle, + * so the wakeups are still functional (Only known case for now is UART) */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -476,6 +479,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) #define HWMOD_BLOCK_WFI (1 << 10) #define HWMOD_FORCE_MSTANDBY (1 << 11) +#define HWMOD_SWSUP_SIDLE_ACT (1 << 12) /* * omap_hwmod._int_flags definitions -- cgit v1.2.3 From 66dde54e978a310c57a40023ff39835fa5ccd7a3 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 May 2013 20:18:39 +0530 Subject: ARM: OMAP2+: hwmod-data: UART IP needs software control to manage sidle modes OMAP UART IP needs software control for slave idle modes based on functional state of the IP. i.e The IP slave idle settings should be set to 'noidle' when being used and then put back to 'smart_idle' when unused. Currently this is handled by the driver with function pointers implemented in platform code. This however breaks in case of device tree because of missing idle handling APIs. Previous patches in this series added a flag HWMOD_SWSUP_SIDLE_ACTIVE which takes care of the mentioned requirement. Hence add the flag for all UART IPs to take advantage of feature supported by framework. Subsequent patches removes the slave idle handling from driver code. Tested-by: Vaibhav Bedia Tested-by: Sourav Poddar Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman # OMAP4/Panda Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 3 +++ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4 ++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 6 +++++- 4 files changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index c8c64b3e1acc..d05fc7b54567 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -512,6 +512,7 @@ struct omap_hwmod omap2xxx_uart1_hwmod = { .mpu_irqs = omap2_uart1_mpu_irqs, .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -531,6 +532,7 @@ struct omap_hwmod omap2xxx_uart2_hwmod = { .mpu_irqs = omap2_uart2_mpu_irqs, .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -550,6 +552,7 @@ struct omap_hwmod omap2xxx_uart3_hwmod = { .mpu_irqs = omap2_uart3_mpu_irqs, .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 01d8f324450a..075f7cc51026 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -1995,6 +1995,7 @@ static struct omap_hwmod am33xx_uart1_hwmod = { .name = "uart1", .class = &uart_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart1_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_wkupdm_ck", @@ -2015,6 +2016,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = { .name = "uart2", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart2_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2042,6 +2044,7 @@ static struct omap_hwmod am33xx_uart3_hwmod = { .name = "uart3", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart3_irqs, .sdma_reqs = uart3_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2062,6 +2065,7 @@ static struct omap_hwmod am33xx_uart4_hwmod = { .name = "uart4", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart4_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2082,6 +2086,7 @@ static struct omap_hwmod am33xx_uart5_hwmod = { .name = "uart5", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart5_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", @@ -2102,6 +2107,7 @@ static struct omap_hwmod am33xx_uart6_hwmod = { .name = "uart6", .class = &uart_class, .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart6_irqs, .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 4083606ea1da..31c7126eb3bb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -490,6 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .mpu_irqs = omap2_uart1_mpu_irqs, .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -508,6 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .mpu_irqs = omap2_uart2_mpu_irqs, .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -526,6 +528,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .mpu_irqs = omap2_uart3_mpu_irqs, .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, @@ -555,6 +558,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, .main_clk = "uart4_fck", + .flags = HWMOD_SWSUP_SIDLE_ACT, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index eaba9dc91a0d..848b6dc67590 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3434,6 +3434,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart1_irqs, .sdma_reqs = omap44xx_uart1_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3462,6 +3463,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart2_irqs, .sdma_reqs = omap44xx_uart2_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3490,7 +3492,8 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart3_irqs, .sdma_reqs = omap44xx_uart3_sdma_reqs, .main_clk = "func_48m_fclk", @@ -3519,6 +3522,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = omap44xx_uart4_irqs, .sdma_reqs = omap44xx_uart4_sdma_reqs, .main_clk = "func_48m_fclk", -- cgit v1.2.3 From e59cd225c0ad280122cb69e04cd66699557875a4 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 May 2013 20:18:40 +0530 Subject: ARM: OMAP2+: serial: Remove the un-used slave idle hooks UART IP idle handling now taken care by runtime pm backend(hwmod) indirectly and OMAP serial driver is also cleaned up accordingly. So remove the un-used slave idle platforms hooks now. Tested-by: Vaibhav Bedia Tested-by: Sourav Poddar Signed-off-by: Rajendra nayak Signed-off-by: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman # OMAP4/Panda Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/serial.c | 31 ------------------------------- 1 file changed, 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 8396b5b7e912..f6601563aa69 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -95,38 +95,9 @@ static void omap_uart_enable_wakeup(struct device *dev, bool enable) omap_hwmod_disable_wakeup(od->hwmods[0]); } -/* - * Errata i291: [UART]:Cannot Acknowledge Idle Requests - * in Smartidle Mode When Configured for DMA Operations. - * WA: configure uart in force idle mode. - */ -static void omap_uart_set_noidle(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *od = to_omap_device(pdev); - - omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); -} - -static void omap_uart_set_smartidle(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *od = to_omap_device(pdev); - u8 idlemode; - - if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) - idlemode = HWMOD_IDLEMODE_SMART_WKUP; - else - idlemode = HWMOD_IDLEMODE_SMART; - - omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); -} - #else static void omap_uart_enable_wakeup(struct device *dev, bool enable) {} -static void omap_uart_set_noidle(struct device *dev) {} -static void omap_uart_set_smartidle(struct device *dev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX @@ -299,8 +270,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; omap_up.flags = UPF_BOOT_AUTOCONF; omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; - omap_up.set_forceidle = omap_uart_set_smartidle; - omap_up.set_noidle = omap_uart_set_noidle; omap_up.enable_wakeup = omap_uart_enable_wakeup; omap_up.dma_rx_buf_size = info->dma_rx_buf_size; omap_up.dma_rx_timeout = info->dma_rx_timeout; -- cgit v1.2.3 From 3260c76055afc6c9396e5ad9f9e599505ea8891f Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 May 2013 20:18:42 +0530 Subject: ARM: OMAP2+: hwmod: Remove sysc slave idle and auto idle apis With the OMAP serial driver sysc cleanup patches in this series, we can now remove the hwmod external apis for sysc fiddling. While at this, also remove unused sysc auto idle api from hwmod code. Tested-by: Vaibhav Bedia Tested-by: Sourav Poddar Signed-off-by: Rajendra nayak Signed-off-by: Santosh Shilimkar Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman # OMAP4/Panda Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 68 ---------------------------------------- arch/arm/mach-omap2/omap_hwmod.h | 3 -- 2 files changed, 71 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5739429894b0..03931425029b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2254,42 +2254,6 @@ static int _idle(struct omap_hwmod *oh) return 0; } -/** - * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit - * @oh: struct omap_hwmod * - * @autoidle: desired AUTOIDLE bitfield value (0 or 1) - * - * Sets the IP block's OCP autoidle bit in hardware, and updates our - * local copy. Intended to be used by drivers that require - * direct manipulation of the AUTOIDLE bits. - * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes - * along the return value from _set_module_autoidle(). - * - * Any users of this function should be scrutinized carefully. - */ -int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) -{ - u32 v; - int retval = 0; - unsigned long flags; - - if (!oh || oh->_state != _HWMOD_STATE_ENABLED) - return -EINVAL; - - spin_lock_irqsave(&oh->_lock, flags); - - v = oh->_sysc_cache; - - retval = _set_module_autoidle(oh, autoidle, &v); - - if (!retval) - _write_sysconfig(v, oh); - - spin_unlock_irqrestore(&oh->_lock, flags); - - return retval; -} - /** * _shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * @@ -3188,38 +3152,6 @@ error: return ret; } -/** - * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode - * @oh: struct omap_hwmod * - * @idlemode: SIDLEMODE field bits (shifted to bit 0) - * - * Sets the IP block's OCP slave idlemode in hardware, and updates our - * local copy. Intended to be used by drivers that have some erratum - * that requires direct manipulation of the SIDLEMODE bits. Returns - * -EINVAL if @oh is null, or passes along the return value from - * _set_slave_idlemode(). - * - * XXX Does this function have any current users? If not, we should - * remove it; it is better to let the rest of the hwmod code handle this. - * Any users of this function should be scrutinized carefully. - */ -int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) -{ - u32 v; - int retval = 0; - - if (!oh) - return -EINVAL; - - v = oh->_sysc_cache; - - retval = _set_slave_idlemode(oh, idlemode, &v); - if (!retval) - _write_sysconfig(v, oh); - - return retval; -} - /** * omap_hwmod_lookup - look up a registered omap_hwmod by name * @name: name of the omap_hwmod to look up diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 8498774b5fb1..0c898f58ac9b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -645,9 +645,6 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); -int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); -int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle); - int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -- cgit v1.2.3 From 7ec892ef5f1bd707e2d5ab128069cb6af75c7f07 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Wed, 10 Apr 2013 19:30:38 +0900 Subject: ARM: dts: Enabling samsung-usb2phy driver for exynos5250 Adding usbphy node for Exynos5250 along with the necessary device data to be parsed. Signed-off-by: Vivek Gautam Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 98dfc3ea5c0b..0673524238a6 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -497,6 +497,21 @@ clock-names = "usbhost"; }; + usbphy@12130000 { + compatible = "samsung,exynos5250-usb2phy"; + reg = <0x12130000 0x100>; + clocks = <&clock 1>, <&clock 285>; + clock-names = "ext_xtal", "usbhost"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbphy-sys { + reg = <0x10040704 0x8>, + <0x10050230 0x4>; + }; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 2b8b2797142c7951e635c6eec5d1705ee9bc45c5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Sun, 19 May 2013 22:12:43 +0200 Subject: ARM: plat-orion: Fix num_resources and id for ge10 and ge11 When platform data were moved from arch/arm/mach-mv78xx0/common.c to arch/arm/plat-orion/common.c with the commit "7e3819d ARM: orion: Consolidate ethernet platform data", there were few typo made on gigabit Ethernet interface ge10 and ge11. This commit writes back their initial value, which allows to use this interfaces again. Signed-off-by: Gregory CLEMENT Acked-by: Andrew Lunn Cc: # v3.0.x Signed-off-by: Jason Cooper --- arch/arm/plat-orion/common.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 251f827271e9..c019b7aaf776 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -383,7 +383,7 @@ static struct resource orion_ge10_shared_resources[] = { static struct platform_device orion_ge10_shared = { .name = MV643XX_ETH_SHARED_NAME, - .id = 1, + .id = 2, .dev = { .platform_data = &orion_ge10_shared_data, }, @@ -398,8 +398,8 @@ static struct resource orion_ge10_resources[] = { static struct platform_device orion_ge10 = { .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 2, + .id = 2, + .num_resources = 1, .resource = orion_ge10_resources, .dev = { .coherent_dma_mask = DMA_BIT_MASK(32), @@ -432,7 +432,7 @@ static struct resource orion_ge11_shared_resources[] = { static struct platform_device orion_ge11_shared = { .name = MV643XX_ETH_SHARED_NAME, - .id = 1, + .id = 3, .dev = { .platform_data = &orion_ge11_shared_data, }, @@ -447,8 +447,8 @@ static struct resource orion_ge11_resources[] = { static struct platform_device orion_ge11 = { .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 2, + .id = 3, + .num_resources = 1, .resource = orion_ge11_resources, .dev = { .coherent_dma_mask = DMA_BIT_MASK(32), -- cgit v1.2.3 From 489e138eec96f529c5e8d4cd3ea45882ecdbf5ca Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 20 May 2013 16:13:27 +0200 Subject: ARM: dts: mvebu: Fix wrong the address reg value for the L2-cache node During the conversion to the internal-regs' subnode, the L2-cache node haven not been converted (due to a wrong choice made by myself during the resolution of the merge conflict when I rebased the commit). This leads to wrong address for L2 cache which prevent it to be used on Armada 370. This commit fix the address reg of the e L2-cache node. Signed-off-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index a1a870364dd8..aee2b1866ce2 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -39,7 +39,7 @@ L2: l2-cache { compatible = "marvell,aurora-outer-cache"; - reg = <0xd0008000 0x1000>; + reg = <0x08000 0x1000>; cache-id-part = <0x100>; wt-override; }; -- cgit v1.2.3 From 9f8466c6e09e62a1d047f2e57d90cd42e46b35c1 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 May 2013 08:44:17 +0100 Subject: ARM: vt8500: Add missing NULL terminator in dt_compat When I tried booting a stih415 Dual core A9 with multi_v7_defconfig, it failed to boot. The issues seems to be changing by enabling or disabling VT8550 platform. Having a quick look at dt_compat list, it seems to miss a NULL terminator, which means of_flat_dt_match will compat check will cross the boundary of dt_compat and fault at some point , which is what was happening in my case. Without this patch if we try to boot multi_v7_defconfig you might notice that some of the platforms might fault if they fall after vt8500 in machine-desc list. Other platforms which fall before vt8500 in mdesc list will not fault. Signed-off-by: Srinivas Kandagatla Acked-by: Tony Prisk Signed-off-by: Olof Johansson --- arch/arm/mach-vt8500/vt8500.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 1dd281efc020..f5c33df7a597 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -173,6 +173,7 @@ static const char * const vt8500_dt_compat[] = { "wm,wm8505", "wm,wm8750", "wm,wm8850", + NULL }; DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") -- cgit v1.2.3 From b98da4db297bad34a5577df36ff4cb2a8fc90923 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 19 May 2013 00:47:39 +0200 Subject: ARM: nomadik: fix IRQ assignment for SMC ethernet The assignment of IRQ for the SMC91x ethernet adapter had two problems making it non-working: - It was not put into the ethernet device node. Let's do this by using the board-specific overlay, so we can make other overlays on other Nomadik boards. - The IRQ number was actually completely wrong, this was the number for NHK8815, not S8815. After this ethernet starts working on the USB S8815. Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/ste-nomadik-s8815.dts | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index b28fbf3408e3..6f82d9368948 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -14,13 +14,19 @@ bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; }; + /* This is where the interrupt is routed on the S8815 board */ + external-bus@34000000 { + ethernet@300 { + interrupt-parent = <&gpio3>; + interrupts = <8 0x1>; + }; + }; + /* Custom board node with GPIO pins to active etc */ usb-s8815 { /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; + gpios = <&gpio3 8 0x1>; }; /* This will bias the MMC/SD card detect line */ mmcsd-gpio { -- cgit v1.2.3 From 8d9849b05154ff6f19f538c2d094ea0f32981bb0 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Mon, 20 May 2013 13:07:19 -0600 Subject: ARM: tegra: defconfig fixes The AK8975 Kconfig option was renamed during the 3.10 merge window. Adjust tegra_defconfig to enable the new name, so it's not missing useful features. Tegra DRM support used to be enabled in the default Tegra configuration, but it now depends on CONFIG_TEGRA_HOST1X which is disabled by default. Enable CONFIG_TEGRA_HOST1X so that DRM support is compiled in again. Signed-off-by: Alexandre Courbot [swarren, squashed Alex's and my changes together] Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/configs/tegra_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index a5f0485133cf..f7ba316164d4 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -153,6 +153,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_DRM=y +CONFIG_TEGRA_HOST1X=y CONFIG_DRM_TEGRA=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set @@ -202,7 +203,7 @@ CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y -CONFIG_SENSORS_AK8975=y +CONFIG_AK8975=y CONFIG_MFD_NVEC=y CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y -- cgit v1.2.3 From aa033810461ee56abbef6cef10aabd6b97f5caee Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 20 May 2013 17:57:16 -0700 Subject: ARM: smp: Drop RCU_NONIDLE usage in cpu_die() Before f7b861b7a6d9 ("arm: Use generic idle loop") ARM would kill the CPU within the rcu idle section. Now that the rcu_idle_enter()/exit() pair have been pushed lower down in the idle loop this is no longer true and so using RCU_NONIDLE here is no longer necessary and also harmful because RCU is not actually idle at this point. Cc: Russell King Acked-by: Paul E. McKenney Signed-off-by: Stephen Boyd Signed-off-by: Linus Torvalds --- arch/arm/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 47ab90563bf4..550d63cef68e 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -251,7 +251,7 @@ void __ref cpu_die(void) * this returns, power and/or clocks can be removed at any point * from this CPU and its cache by platform_cpu_kill(). */ - RCU_NONIDLE(complete(&cpu_died)); + complete(&cpu_died); /* * Ensure that the cache lines associated with that completion are -- cgit v1.2.3 From 5f10428e4a6d99cc019270c51ad5a33fb38addeb Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 16 May 2013 12:14:59 +0900 Subject: ARM: shmobile: marzen: Use error values in usb_power_* This patch updates the marzen board code as if USB PHY isn't enabled they phy will have a value set by ERR_PTR() rather than be NULL. Without this patch a NULL pointer dereference and kernel panic occurs on initialisation of USB on marzen. This resolves a regression introduced in 3.10-rc1 by b7fa5c2aec5be083eb2719b405089703608e9bc6 ("usb: phy: return -ENXIO when PHY layer isn't enabled"). Tested-by: Nguyen Hong Ky Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-marzen.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 91052855cc12..b9594e911ce7 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -212,8 +212,8 @@ static struct platform_device *marzen_devices[] __initdata = { static struct usb_phy *phy; static int usb_power_on(struct platform_device *pdev) { - if (!phy) - return -EIO; + if (IS_ERR(phy)) + return PTR_ERR(phy); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); @@ -225,7 +225,7 @@ static int usb_power_on(struct platform_device *pdev) static void usb_power_off(struct platform_device *pdev) { - if (!phy) + if (IS_ERR(phy)) return; usb_phy_shutdown(phy); -- cgit v1.2.3 From 934fc24df10abfd5aff533d0d044a17669d77d79 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 15 May 2013 10:46:30 +0100 Subject: ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handling Make the SHA1 asm code ABI conformant by making sure all stack accesses occur above the stack pointer. Origin: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2 Signed-off-by: Ard Biesheuvel Acked-by: Nicolas Pitre Cc: stable@vger.kernel.org Signed-off-by: Russell King --- arch/arm/crypto/sha1-armv4-large.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S index 92c6eed7aac9..99207c45ec10 100644 --- a/arch/arm/crypto/sha1-armv4-large.S +++ b/arch/arm/crypto/sha1-armv4-large.S @@ -195,6 +195,7 @@ ENTRY(sha1_block_data_order) add r3,r3,r10 @ E+=F_00_19(B,C,D) cmp r14,sp bne .L_00_15 @ [((11+4)*5+2)*3] + sub sp,sp,#25*4 #if __ARM_ARCH__<7 ldrb r10,[r1,#2] ldrb r9,[r1,#3] @@ -290,7 +291,6 @@ ENTRY(sha1_block_data_order) add r3,r3,r10 @ E+=F_00_19(B,C,D) ldr r8,.LK_20_39 @ [+15+16*4] - sub sp,sp,#25*4 cmn sp,#0 @ [+3], clear carry to denote 20_39 .L_20_39_or_60_79: ldr r9,[r14,#15*4] -- cgit v1.2.3 From 4ca46c5e1f38e32c90247686e9e17dae213ecbdb Mon Sep 17 00:00:00 2001 From: Steven Capper Date: Thu, 16 May 2013 17:16:11 +0100 Subject: ARM: 7727/1: remove the .vm_mm value from gate_vma If one reads /proc/$PID/smaps, the mmap_sem belonging to the address space of the task being examined is locked for reading. All the pages of the vmas belonging to the task's address space are then walked with this lock held. If a gate_vma is present in the architecture, it too is examined by the fs/proc/task_mmu.c code. As gate_vma doesn't belong to the address space of the task though, its pages are not walked. A recent cleanup (commit f6604efe) of the gate_vma initialisation code set the vm_mm value to &init_mm. Unfortunately a non-NULL vm_mm value in the gate_vma will cause the task_mmu code to attempt to walk the pages of the gate_vma (with no mmap-sem lock held). If one enables Transparent Huge Page support and vm debugging, this will then cause OOPses as pmd_trans_huge_lock is called without mmap_sem being locked. This patch removes the .vm_mm value from gate_vma, restoring the original behaviour of the task_mmu code. Signed-off-by: Steve Capper Signed-off-by: Russell King --- arch/arm/kernel/process.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index f21970316836..282de4826abb 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -411,7 +411,6 @@ static struct vm_area_struct gate_vma = { .vm_start = 0xffff0000, .vm_end = 0xffff0000 + PAGE_SIZE, .vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC, - .vm_mm = &init_mm, }; static int __init gate_vma_init(void) -- cgit v1.2.3 From f27d6e172367a424ecf9d373062a820338671277 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 16 May 2013 19:38:51 +0100 Subject: ARM: 7729/1: vfp: ensure VFP_arch is non-zero when VFP is not supported Commit d3f79584a8b5 ("ARM: cleanup undefined instruction entry code") improved the register scheduling when handling undefined instructions. A side effect of this is that r5 is now used as a temporary, whilst the VFP probing code relies on r5 containing a non-zero value when VFP is not supported. This patch fixes the VFP detection code so that we don't rely on the contents of r5. Without this patch, Linux dies loudly on CPUs without VFP support. Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/vfp/entry.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 323ce1a62bbf..46e17492fd1f 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -60,7 +60,7 @@ ENTRY(vfp_testing_entry) str r11, [r10, #TI_PREEMPT] #endif ldr r0, VFP_arch_address - str r5, [r0] @ known non-zero value + str r0, [r0] @ set to non-zero value mov pc, r9 @ we have handled the fault ENDPROC(vfp_testing_entry) -- cgit v1.2.3 From cc9a3e99949af4bcaf9027fc57f824b595a5fcac Mon Sep 17 00:00:00 2001 From: Jiada Wang Date: Mon, 20 May 2013 21:51:51 +0900 Subject: ARM i.MX6q: fix for ldb_di_sels As pll5_video_div has been introduced to represent the clock generated from post-divider for video. Instead of pll5_video, pll5_video_div should be proper root clock for ldb_di_sel. Signed-off-by: Jiada Wang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index dda9a2bd3acb..ba2de54a39db 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -188,7 +188,7 @@ static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m" static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; -static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; +static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -- cgit v1.2.3 From 37523dc5ec2fead0eb5235fd9334f0419013a1f2 Mon Sep 17 00:00:00 2001 From: Jonas Andersson Date: Thu, 23 May 2013 13:38:05 +0200 Subject: ARM: dts: imx: fix clocks for cspi The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor. Signed-off-by: Jonas Andersson Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 12 ++++++------ arch/arm/boot/dts/imx27.dtsi | 6 +++--- arch/arm/boot/dts/imx51.dtsi | 2 +- arch/arm/boot/dts/imx53.dtsi | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index d2550e0bca24..701153992c69 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -141,8 +141,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x43fa4000 0x4000>; - clocks = <&clks 62>; - clock-names = "ipg"; + clocks = <&clks 62>, <&clks 62>; + clock-names = "ipg", "per"; interrupts = <14>; status = "disabled"; }; @@ -182,8 +182,8 @@ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50004000 0x4000>; interrupts = <0>; - clocks = <&clks 80>; - clock-names = "ipg"; + clocks = <&clks 80>, <&clks 80>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -210,8 +210,8 @@ #size-cells = <0>; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; reg = <0x50010000 0x4000>; - clocks = <&clks 79>; - clock-names = "ipg"; + clocks = <&clks 79>, <&clks 79>; + clock-names = "ipg", "per"; interrupts = <13>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index ff4bd4873edf..75bd11386516 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -131,7 +131,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000e000 0x1000>; interrupts = <16>; - clocks = <&clks 53>, <&clks 0>; + clocks = <&clks 53>, <&clks 53>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -142,7 +142,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x1000f000 0x1000>; interrupts = <15>; - clocks = <&clks 52>, <&clks 0>; + clocks = <&clks 52>, <&clks 52>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -223,7 +223,7 @@ compatible = "fsl,imx27-cspi"; reg = <0x10017000 0x1000>; interrupts = <6>; - clocks = <&clks 51>, <&clks 0>; + clocks = <&clks 51>, <&clks 51>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 21bb786c5b31..53fdde69bbf4 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -631,7 +631,7 @@ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 845982eaac22..eb83aa039b8b 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -714,7 +714,7 @@ compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; - clocks = <&clks 55>, <&clks 0>; + clocks = <&clks 55>, <&clks 55>; clock-names = "ipg", "per"; status = "disabled"; }; -- cgit v1.2.3 From 029efddab6967f755c21f47b0bc456f1a546805f Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 24 May 2013 00:59:16 +0200 Subject: ARM: at91: at91sam9n12: move external irq declatation to DT Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12.dtsi | 1 + arch/arm/mach-at91/at91sam9n12.c | 6 ------ 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 3de8e6dfbcb1..8d25f889928e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -57,6 +57,7 @@ compatible = "atmel,at91rm9200-aic"; interrupt-controller; reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; }; ramc0: ramc@ffffe800 { diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 13cdbcd48f51..c7d670d11802 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -223,13 +223,7 @@ static void __init at91sam9n12_map_io(void) at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); } -void __init at91sam9n12_initialize(void) -{ - at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); -} - AT91_SOC_START(at91sam9n12) .map_io = at91sam9n12_map_io, .register_clocks = at91sam9n12_register_clocks, - .init = at91sam9n12_initialize, AT91_SOC_END -- cgit v1.2.3 From f6d35d67d0a5c159f767a20f4fcc1d295a7314b1 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 23 May 2013 18:01:21 +0200 Subject: ARM: at91/dt: fix macb pinctrl_macb_rmii_mii_alt definition The PA24 pin is wrongly assigned to peripheral B. In the current config there is 2 ETX3 pins (PA11 and PA24) and no ETXER pin (PA22). Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre Cc: stable # 3.8+ --- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 70b5ccbac234..84c4bef2d726 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -264,7 +264,7 @@ atmel,pins = <0 10 0x2 0x0 /* PA10 periph B */ 0 11 0x2 0x0 /* PA11 periph B */ - 0 24 0x2 0x0 /* PA24 periph B */ + 0 22 0x2 0x0 /* PA22 periph B */ 0 25 0x2 0x0 /* PA25 periph B */ 0 26 0x2 0x0 /* PA26 periph B */ 0 27 0x2 0x0 /* PA27 periph B */ -- cgit v1.2.3 From 144ea15e4fefbee14a7dcb05c7cd0822fda3ebf6 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Thu, 23 May 2013 10:18:48 +0000 Subject: ARM: at91/sama5: fix incorrect PMC pcr div definition Signed-off-by: Josh Wu Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Ludovic Desroches Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/include/mach/at91_pmc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 31df12029c4e..2bd7f51b0b82 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base; #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ +#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ +#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ +#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #endif -- cgit v1.2.3 From 68a433f18c0574b50c5952978ca95b0db7347174 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 25 May 2013 06:27:29 +0900 Subject: ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC This patch extends exynos_init_time() function to handle Exynos4210 rev0 SoC, which differs in availability of system timers and needs different clocksource initialization. This makes it possible to use exynos_init_time() function as init_time callback for all Exynos-based boards, including Universal_C210, which originally had to use samsung_timer_init(). Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 3 ++- arch/arm/mach-exynos/common.c | 30 +++++++++++++++++++++++++++++- arch/arm/mach-exynos/common.h | 2 ++ arch/arm/mach-exynos/mach-universal_c210.c | 5 ++--- 4 files changed, 35 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d19edff0ea6e..ff18fc2ea46f 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -250,6 +250,7 @@ config MACH_ARMLEX4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_EXYNOS4210 select EXYNOS4_SETUP_FIMC select EXYNOS4_SETUP_FIMD0 @@ -281,7 +282,6 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_TV select S5P_GPIO_INT select S5P_SETUP_MIPIPHY - select SAMSUNG_HRT help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -410,6 +410,7 @@ config MACH_EXYNOS4_DT depends on ARCH_EXYNOS4 select ARM_AMBA select CLKSRC_OF + select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD select PINCTRL diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 745e304ad0de..a2d20120e9fc 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -10,12 +10,14 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -302,6 +304,13 @@ static struct map_desc exynos5440_iodesc0[] __initdata = { }, }; +static struct samsung_pwm_variant exynos4_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = 0, +}; + void exynos4_restart(char mode, const char *cmd) { __raw_writel(0x1, S5P_SWRESET); @@ -442,8 +451,20 @@ static void __init exynos5440_map_io(void) iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); } +void __init exynos_set_timer_source(u8 channels) +{ + exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + exynos4_pwm_variant.output_mask &= ~channels; +} + void __init exynos_init_time(void) { + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC, + EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC, + EXYNOS4_IRQ_TIMER4_VIC, + }; + if (of_have_populated_dt()) { #ifdef CONFIG_OF of_clk_init(NULL); @@ -455,7 +476,14 @@ void __init exynos_init_time(void) exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); #endif - mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); +#ifdef CONFIG_CLKSRC_SAMSUNG_PWM + if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &exynos4_pwm_variant); + else +#endif + mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, + EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); } } diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 60dd35cc01a6..11fc1e29819b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -32,6 +32,8 @@ void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); void exynos_firmware_init(void); +void exynos_set_timer_source(u8 channels); + #ifdef CONFIG_PM_GENERIC_DOMAINS int exynos_pm_late_initcall(void); #else diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 327d50d4681d..74ddb2b55614 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include @@ -1094,7 +1093,7 @@ static void __init universal_map_io(void) { exynos_init_io(NULL, 0); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); + exynos_set_timer_source(BIT(2) | BIT(4)); xxti_f = 0; xusbxti_f = 24000000; } @@ -1154,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .init_machine = universal_machine_init, .init_late = exynos_init_late, - .init_time = samsung_timer_init, + .init_time = exynos_init_time, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END -- cgit v1.2.3 From 1ba830c9997214a7fbe4d91cf238793764620e3b Mon Sep 17 00:00:00 2001 From: Jungseok Lee Date: Sat, 25 May 2013 06:33:03 +0900 Subject: ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC This patch fixes software reset logic. Software reset applies only to powered-on domains in SOC because software reset to all domains causes reboot failure. Signed-off-by: Jungseok Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index a2d20120e9fc..027c9e7f0d13 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -326,9 +326,16 @@ void exynos5_restart(char mode, const char *cmd) val = 0x1; addr = EXYNOS_SWRESET; } else if (of_machine_is_compatible("samsung,exynos5440")) { + u32 status; np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + + addr = of_iomap(np, 0) + 0xbc; + status = __raw_readl(addr); + addr = of_iomap(np, 0) + 0xcc; - val = (0xfff << 20) | (0x1 << 16); + val = __raw_readl(addr); + + val = (val & 0xffff0000) | (status & 0xffff); } else { pr_err("%s: cannot support non-DT\n", __func__); return; -- cgit v1.2.3 From 15f504f0c2038b9a0f1569c9ce34def61f0c65be Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 25 May 2013 06:49:43 +0900 Subject: ARM: SAMSUNG: Add names to fimd0 IRQ resources Since commit 1977e6d8 (drm/exynos: change the method for getting the interrupt) the Exynos DRM FIMD driver requires IRQ resources to be named. This patch fixes probe failure in non-DT cases by adding appropriate resource names to fimd0 platform device. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/devs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 30c2fe243f76..0f9c3f431a5f 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = { #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), - [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), - [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), - [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), + [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"), + [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"), + [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"), }; struct platform_device s5p_device_fimd0 = { -- cgit v1.2.3 From 2c06897e4597b1cd68ef29e4145917a751c2b4cd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 16 May 2013 12:15:35 +0100 Subject: ARM: ux500: Only configure wake-up reasons on ux500 based platforms Multiplatform calls all enabled platforms' initcalls. In the ux500_idle_init() initcall we call into the DBx500-PRCMU which in turn executes some ux500 specific register reads/writes. When running on some !ux500 platforms this ends up causing a kernel Oops. This patch ensures the PRCMU call is only invoked when running on ux500 based platforms. Reported-by: Rob Herring Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpuidle.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index 317a2be129fb..a45dd09daed9 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -21,6 +21,7 @@ #include #include "db8500-regs.h" +#include "id.h" static atomic_t master = ATOMIC_INIT(0); static DEFINE_SPINLOCK(master_lock); @@ -114,6 +115,9 @@ static struct cpuidle_driver ux500_idle_driver = { int __init ux500_idle_init(void) { + if (!(cpu_is_u8500_family() || cpu_is_ux540_family())) + return -ENODEV; + /* Configure wake up reasons */ prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | PRCMU_WAKEUP(ABB)); -- cgit v1.2.3 From 67b7c75e1a42f8288450203cd80a26b11dab8582 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 24 May 2013 12:22:19 +0100 Subject: ARM: ux500: Provide supplies for AUX1, AUX2 and AUX3 This patch fixes a bug introduced in the v3.10 merge window. The AB8500 External Regulator driver has recently landed upstream, which registers each of the 3 external regulators located on the AB8500. If these regulators are marked as 'always on', there is a potential for power-loss. If they're not and are seemingly unused the Regulator subsystem will attempt to disable them to save power. This causes an issue for AUX1, AUX2 and AUX3 as they obtain their power from EXT3. So we're specifying that here to prevent EXT3 from being powered down. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-regulators.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 33c353bc1c4a..d6b7c8556fa1 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -374,6 +374,7 @@ static struct ab8500_regulator_reg_init ab8500_reg_init[] = { static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { /* supplies to the display/camera */ [AB8500_LDO_AUX1] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-DISPLAY", .min_uV = 2800000, @@ -387,6 +388,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { }, /* supplies to the on-board eMMC */ [AB8500_LDO_AUX2] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-eMMC1", .min_uV = 1100000, @@ -402,6 +404,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { }, /* supply for VAUX3, supplies to SDcard slots */ [AB8500_LDO_AUX3] = { + .supply_regulator = "ab8500-ext-supply3", .constraints = { .name = "V-MMC-SD", .min_uV = 1100000, -- cgit v1.2.3 From b134dc3feaa5136b376c7d2658bbe156bea19e63 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 17 May 2013 18:24:28 +0200 Subject: ARM: EXYNOS: Fix EINT wake-up mask configuration when pinctrl is used On DT-enabled systems pinctrl-exynos driver is responsible for handling of wake-up EINT interrupts. This patch adjusts wake-up mask configuration code to take wake-up mask value from pinctrl-exynos driver on DT-enabled systems. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Tested-by: Doug Anderson Signed-off-by: Linus Walleij --- arch/arm/mach-exynos/include/mach/pm-core.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 7dbbfec13ea5..296090e7f423 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -18,8 +18,15 @@ #ifndef __ASM_ARCH_PM_CORE_H #define __ASM_ARCH_PM_CORE_H __FILE__ +#include #include +#ifdef CONFIG_PINCTRL_EXYNOS +extern u32 exynos_get_eint_wake_mask(void); +#else +static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } +#endif + static inline void s3c_pm_debug_init_uart(void) { /* nothing here yet */ @@ -27,7 +34,12 @@ static inline void s3c_pm_debug_init_uart(void) static inline void s3c_pm_arch_prepare_irqs(void) { - __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); + u32 eintmask = s3c_irqwake_eintmask; + + if (of_have_populated_dt()) + eintmask = exynos_get_eint_wake_mask(); + + __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK); __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); } -- cgit v1.2.3 From e89b4058096569c999fa599370162022a5a2b3d2 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 21 May 2013 19:41:48 +0200 Subject: ARM: Kirkwood: TS219: Fix crash by double PCIe instantiation When creating the DT based boards-ts219.c the none DT ts219-setup.c was used as a template. This includes a lateinit() call to initialize the PCIe bus. The code makes use of machine_is_ts219() which is never true on DT, so a FIXME was added and the code left as is. This was unproblematic until b73690c8f8b5d: "ARM: Kirkwood: Support basic hotplug for PCI-E" which changes the way the PCIe bus is initialized. The non-DT ts219-setup.c now crashes during boot. The lateinit() call in the DT boards-ts219.c is being called, machine_is_ts219() is true and so the PCIe is initialized a second time. This patch removes the useless, and now clearly dangerous, code from boards-ts219.c, making ts219-setup.c work again. Signed-off-by: Andrew Lunn Cc: # v3.9.x Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/board-ts219.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index acb0187c7ee1..4695d5f35fc9 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -41,13 +41,3 @@ void __init qnap_dt_ts219_init(void) pm_power_off = qnap_tsx1x_power_off; } - -/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */ -static int __init ts219_pci_init(void) -{ - if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} -subsys_initcall(ts219_pci_init); -- cgit v1.2.3 From b60b61d41220c8d34e2c62a748bc78bc5d40585e Mon Sep 17 00:00:00 2001 From: Nadav Haklai Date: Thu, 23 May 2013 10:54:02 +0200 Subject: ARM: mvebu: Fix bug in coherency fabric low level init function When adding CPU to the SMP group and enabling the coherency on this CPU we must protect the register access. The previous implementation claims to be atomic but doesn't provide any protection against parallel access to the coherency fabric control and configuration registers. This patch fixes this by using the ldrex and strex mechanism. This method should be used in all accesses to those registers. [gregory.clement@free-electrons.com: fixed the commit's topic] Signed-off-by: Nadav Haklai Signed-off-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/coherency_ll.S | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 53e8391192cd..5476669ba905 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET - ldr r2, [r3] +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b /* Enable coherency on CPU - Atomic */ - add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET - ldr r2, [r3] + add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b dsb -- cgit v1.2.3 From da9d0fbf5e9aa47492a19588bd0efd18d6d172e0 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 9 May 2013 13:58:19 -0700 Subject: ARM: exynos: defconfig update This turns on a number of configs that are useful on the Chromebook, but also good to have on in general: * USB host and MMC drivers(!) * I2C GPIO arbitration driver * CYAPA trackpad driver * simplefb * CROS EC and keyboard drivers * S5M8767 driver * MAX77686 drivers * MAX8997 driver * DEVTMPFS + mount * DM_CRYPT (as module) * CRYPTOLOOP * HIGHMEM * PRINTK timestamps This also turns off DEBUG_LL, and switches the hardcoded Samsung lowlevel uart to uart 3 (which is only used to show the "uncompressing kernel" message at boot, it seems). Signed-off-by: Olof Johansson Reviewed-by: Doug Anderson Tested-by: Tushar Behera Acked-by: Kukjin Kim --- arch/arm/configs/exynos_defconfig | 54 +++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index e40b435d204e..227abf9cc601 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -1,4 +1,4 @@ -CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BLK_DEV_INITRD=y @@ -7,17 +7,18 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_LOWLEVEL_UART_PORT=3 CONFIG_S3C24XX_PWM=y CONFIG_ARCH_EXYNOS5=y CONFIG_MACH_EXYNOS4_DT=y -CONFIG_MACH_EXYNOS5_DT=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" @@ -30,35 +31,58 @@ CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_RFKILL_REGULATOR=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y CONFIG_SMSC911X=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_CYAPA=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_S3C2410=y +CONFIG_DEBUG_GPIO=y # CONFIG_HWMON is not set +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_SEC_CORE=y CONFIG_MFD_TPS65090=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y CONFIG_EXYNOS_VIDEO=y CONFIG_EXYNOS_MIPI_DSI=y CONFIG_EXYNOS_DP=y @@ -67,6 +91,20 @@ CONFIG_FONTS=y CONFIG_FONT_7x14=y CONFIG_LOGO=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_PHY=y +CONFIG_SAMSUNG_USB2PHY=y +CONFIG_SAMSUNG_USB3PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y @@ -79,6 +117,7 @@ CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y @@ -87,6 +126,5 @@ CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_SHA256=y CONFIG_CRC_CCITT=y -- cgit v1.2.3 From 2d403f7b198163d14a37ab79de33e27e390bb3b1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 30 May 2013 12:44:47 -0700 Subject: ARM: OMAP3: Fix iva2_pwrdm settings for 3703 Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists) changed PM to not access IVA registers on omaps that don't have them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm will stay on and block deeper idle states. It seems that the only part of the reset that may not be needed is the setting of the iva2 boot mode to idle. But as that register seems to be there and is harmless if no iva2 is on the SoC, it's probably safest to do the complete reset. Acked-by: Mark A. Greer Acked-by: Kevin Hilman Tested-by: Yegor Yefremov Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index c01859398b54..5a2d8034c8de 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void) /* Clear any pending PRCM interrupts */ omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - if (omap3_has_iva()) - omap3_iva_idle(); + /* + * We need to idle iva2_pwrdm even on am3703 with no iva2. + */ + omap3_iva_idle(); omap3_d2d_idle(); } -- cgit v1.2.3 From 13731d862cf5219216533a3b0de052cee4cc5038 Mon Sep 17 00:00:00 2001 From: Jongsung Kim Date: Wed, 29 May 2013 22:07:39 -0600 Subject: ARM: bcm2835: override the HW UART periphid Stephen Warren reported the recent commit 78506f2 (add support for extended FIFO-size of PL011-r1p5) breaks the serial port on the BCM2835 ARM SoC. A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for this compatibility issue, this patch overrides the HW UART periphid register values with the actually compatible UART periphid 0x00241011 (r1p3 or r1p4). Reported-by: Stephen Warren Signed-off-by: Jongsung Kim Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm2835.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index f0052dccf9a8..1e12aeff403b 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -44,6 +44,7 @@ reg = <0x7e201000 0x1000>; interrupts = <2 25>; clock-frequency = <3000000>; + arm,primecell-periphid = <0x00241011>; }; gpio: gpio { -- cgit v1.2.3 From a08b9bc586a7810cdebbc316d5cbaed56a2a04a9 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 31 May 2013 17:01:54 -0400 Subject: ARM: imx: clk-imx6q: AXI clock select index is incorrect The AXI clock mux should be as below: 00: periph; 01: pll2_pfd2_396m; 10: periph; 11: pll3_pfd1_540m; Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index ba2de54a39db..4e3148ce852d 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -181,7 +181,7 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; -- cgit v1.2.3 From e8180dcaa8470ceca21109f143876fdcd9fe050a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 9 May 2013 00:28:06 +0200 Subject: ARM: KVM: prevent NULL pointer dereferences with KVM VCPU ioctl Some ARM KVM VCPU ioctls require the vCPU to be properly initialized with the KVM_ARM_VCPU_INIT ioctl before being used with further requests. KVM_RUN checks whether this initialization has been done, but other ioctls do not. Namely KVM_GET_REG_LIST will dereference an array with index -1 without initialization and thus leads to a kernel oops. Fix this by adding checks before executing the ioctl handlers. [ Removed superflous comment from static function - Christoffer ] Changes from v1: * moved check into a static function with a meaningful name Signed-off-by: Andre Przywara Signed-off-by: Christoffer Dall --- arch/arm/kvm/arm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 37d216d814cd..ef1703b9587b 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -492,6 +492,11 @@ static void vcpu_pause(struct kvm_vcpu *vcpu) wait_event_interruptible(*wq, !vcpu->arch.pause); } +static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.target >= 0; +} + /** * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code * @vcpu: The VCPU pointer @@ -508,8 +513,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) int ret; sigset_t sigsaved; - /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */ - if (unlikely(vcpu->arch.target < 0)) + if (unlikely(!kvm_vcpu_initialized(vcpu))) return -ENOEXEC; ret = kvm_vcpu_first_run_init(vcpu); @@ -710,6 +714,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp, case KVM_SET_ONE_REG: case KVM_GET_ONE_REG: { struct kvm_one_reg reg; + + if (unlikely(!kvm_vcpu_initialized(vcpu))) + return -ENOEXEC; + if (copy_from_user(®, argp, sizeof(reg))) return -EFAULT; if (ioctl == KVM_SET_ONE_REG) @@ -722,6 +730,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, struct kvm_reg_list reg_list; unsigned n; + if (unlikely(!kvm_vcpu_initialized(vcpu))) + return -ENOEXEC; + if (copy_from_user(®_list, user_list, sizeof(reg_list))) return -EFAULT; n = reg_list.n; -- cgit v1.2.3 From d4cb9df5d1f79950b34e78ec5d1b1b59d6e9c7b7 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 14 May 2013 12:11:34 +0100 Subject: ARM: KVM: be more thorough when invalidating TLBs The KVM/ARM MMU code doesn't take care of invalidating TLBs before freeing a {pte,pmd} table. This could cause problems if the page is reallocated and then speculated into by another CPU. Reported-by: Catalin Marinas Signed-off-by: Marc Zyngier Acked-by: Catalin Marinas Signed-off-by: Christoffer Dall --- arch/arm/kvm/mmu.c | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 965706578f13..84ba67b982c0 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector; static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) { - kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa); + /* + * This function also gets called when dealing with HYP page + * tables. As HYP doesn't have an associated struct kvm (and + * the HYP page tables are fairly static), we don't do + * anything there. + */ + if (kvm) + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa); } static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, @@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) return p; } -static void clear_pud_entry(pud_t *pud) +static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) { pmd_t *pmd_table = pmd_offset(pud, 0); pud_clear(pud); + kvm_tlb_flush_vmid_ipa(kvm, addr); pmd_free(NULL, pmd_table); put_page(virt_to_page(pud)); } -static void clear_pmd_entry(pmd_t *pmd) +static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr) { pte_t *pte_table = pte_offset_kernel(pmd, 0); pmd_clear(pmd); + kvm_tlb_flush_vmid_ipa(kvm, addr); pte_free_kernel(NULL, pte_table); put_page(virt_to_page(pmd)); } @@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd) return page_count(pmd_page) == 1; } -static void clear_pte_entry(pte_t *pte) +static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr) { if (pte_present(*pte)) { kvm_set_pte(pte, __pte(0)); put_page(virt_to_page(pte)); + kvm_tlb_flush_vmid_ipa(kvm, addr); } } @@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte) return page_count(pte_page) == 1; } -static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size) +static void unmap_range(struct kvm *kvm, pgd_t *pgdp, + unsigned long long start, u64 size) { pgd_t *pgd; pud_t *pud; @@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size) } pte = pte_offset_kernel(pmd, addr); - clear_pte_entry(pte); + clear_pte_entry(kvm, pte, addr); range = PAGE_SIZE; /* If we emptied the pte, walk back up the ladder */ if (pte_empty(pte)) { - clear_pmd_entry(pmd); + clear_pmd_entry(kvm, pmd, addr); range = PMD_SIZE; if (pmd_empty(pmd)) { - clear_pud_entry(pud); + clear_pud_entry(kvm, pud, addr); range = PUD_SIZE; } } @@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void) mutex_lock(&kvm_hyp_pgd_mutex); if (boot_hyp_pgd) { - unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE); - unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); + unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE); + unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); kfree(boot_hyp_pgd); boot_hyp_pgd = NULL; } if (hyp_pgd) - unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); + unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE); kfree(init_bounce_page); init_bounce_page = NULL; @@ -200,9 +211,10 @@ void free_hyp_pgds(void) if (hyp_pgd) { for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE) - unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE) - unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE); + kfree(hyp_pgd); hyp_pgd = NULL; } @@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) */ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) { - unmap_range(kvm->arch.pgd, start, size); + unmap_range(kvm, kvm->arch.pgd, start, size); } /** @@ -675,7 +687,6 @@ static void handle_hva_to_gpa(struct kvm *kvm, static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data) { unmap_stage2_range(kvm, gpa, PAGE_SIZE); - kvm_tlb_flush_vmid_ipa(kvm, gpa); } int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) -- cgit v1.2.3 From 768dc16397fb18c9de209cbcb84d890b8279faa7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 28 May 2013 17:17:45 +0200 Subject: arm: omap2: fix AM33xx hwmod infos for UART2 The UART2 hwmod structure is pointing to the EDMA channels of UART1, which doesn't look right. This patch fixes this by making the UART2 hwmod structure to a new structure that lists the EDMA channels to be used by the UART2. Signed-off-by: Thomas Petazzoni Acked-by: Vaibhav Hiremath [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 075f7cc51026..69337af748cc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -2007,6 +2007,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = { }, }; +/* uart2 */ +static struct omap_hwmod_dma_info uart2_edma_reqs[] = { + { .name = "tx", .dma_req = 28, }, + { .name = "rx", .dma_req = 29, }, + { .dma_req = -1 } +}; + static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { { .irq = 73 + OMAP_INTC_START, }, { .irq = -1 }, @@ -2018,7 +2025,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = { .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, .mpu_irqs = am33xx_uart2_irqs, - .sdma_reqs = uart1_edma_reqs, + .sdma_reqs = uart2_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { -- cgit v1.2.3 From 00dddcaa51f997cdc6dbae3303a31024e29a0fc0 Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Tue, 28 May 2013 10:24:57 +0200 Subject: ARM: dts: AM33xx: Fix properties on gpmc node The gpmc driver is actually looking for "gpmc,num-cs" and "gpmc,num-waitpins" properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by: Lars Poeschel Acked-by: Peter Korsgaard Acked-by: Pekon Gupta Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 1460d9b88adf..8e1248f01fab 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -409,8 +409,8 @@ ti,hwmods = "gpmc"; reg = <0x50000000 0x2000>; interrupts = <100>; - num-cs = <7>; - num-waitpins = <2>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; -- cgit v1.2.3 From 1e68f43b7dcf0e5eee10baeb3cbe4e1ca59db9fd Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 24 May 2013 17:24:21 -0700 Subject: ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Special thanks to Nishanth Menon for the review and catching some major flaws in earlier versions. Tested on OMAP4430/Panda and OMAP4460/Panda-ES. Cc: Nishanth Menon Cc: Tony Lindgren Signed-off-by: Kevin Hilman Acked-by: Grygorii Strashko [benoit.cousson@linaro.org: Slightly change the subject to align board name with file name] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-common.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/omap4-sdp.dts | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 03bd60deb52b..eeb734e25709 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -56,9 +56,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins @@ -66,6 +80,12 @@ &tpd12s015_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a35d9cd58063..98505a2ef162 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -142,9 +142,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -179,6 +193,12 @@ >; }; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ -- cgit v1.2.3 From 8341613afbc8d65bca8c81158edfb49f36b7ad92 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 17 Apr 2013 18:23:15 -0500 Subject: ARM: dts: OMAP5: Fix missing PWM capability to timer nodes OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM. The PWM capability property is missing from the node definitions of couple of timers. Add ti,timer-pwm attribute for timer 5, 6, 8 and 11. Signed-off-by: Suman Anna [benoit.cousson@linaro.org: Update changelog and subject to highlight the fix] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 3dd7ff825828..635cae283011 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -538,6 +538,7 @@ interrupts = <0 41 0x4>; ti,hwmods = "timer5"; ti,timer-dsp; + ti,timer-pwm; }; timer6: timer@4013a000 { @@ -574,6 +575,7 @@ reg = <0x4803e000 0x80>; interrupts = <0 45 0x4>; ti,hwmods = "timer9"; + ti,timer-pwm; }; timer10: timer@48086000 { @@ -581,6 +583,7 @@ reg = <0x48086000 0x80>; interrupts = <0 46 0x4>; ti,hwmods = "timer10"; + ti,timer-pwm; }; timer11: timer@48088000 { -- cgit v1.2.3 From 5600a8485603b240790005b9b58de4c4f6ada69d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 22 May 2013 19:47:05 +0900 Subject: ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 Update the CMT clockevent rating from 125 to 80. This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1 introduced by f7db706b132f11c79ae1d74b2382e0926cf31644 ("ARM: 7674/1: smp: Avoid dummy clockevent being preferred over real"). The patch noted above reduces the rating of dummy clockevent from 400 to 100. This patch reduces the rating of CMT so that it is once again less than that of the dummy clockevent. Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh73a0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index fdf3894b1cc3..9696f3646864 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", .channel_offset = 0x10, .timer_bit = 0, - .clockevent_rating = 125, + .clockevent_rating = 80, .clocksource_rating = 125, }; -- cgit v1.2.3 From 275236797916924103e133e3d7a7ea777c951273 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 29 May 2013 16:57:30 +0100 Subject: ARM: 7737/1: fix kernel decompressor compilation error with CONFIG_DEBUG_SEMIHOSTING Selecting this option produces: AS arch/arm/boot/compressed/debug.o arch/arm/boot/compressed/debug.S:4:33: fatal error: mach/debug-macro.S: No such file or directory compilation terminated. make[3]: *** [arch/arm/boot/compressed/debug.o] Error 1 The semihosting support cannot be modelled into a senduart macro as it requires memory space for argument passing. So the CONFIG_DEBUG_LL_INCLUDE may not have any sensible value and the include directive should be omitted. While at it, let's add proper semihosting output support to the decompressor. Signed-off-by: Nicolas Pitre Acked-by: Shawn Guo Signed-off-by: Russell King --- arch/arm/boot/compressed/debug.S | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S index 6e8382d5b7a4..5392ee63338f 100644 --- a/arch/arm/boot/compressed/debug.S +++ b/arch/arm/boot/compressed/debug.S @@ -1,6 +1,8 @@ #include #include +#ifndef CONFIG_DEBUG_SEMIHOSTING + #include CONFIG_DEBUG_LL_INCLUDE ENTRY(putc) @@ -10,3 +12,29 @@ ENTRY(putc) busyuart r3, r1 mov pc, lr ENDPROC(putc) + +#else + +ENTRY(putc) + adr r1, 1f + ldmia r1, {r2, r3} + add r2, r2, r1 + ldr r1, [r2, r3] + strb r0, [r1] + mov r0, #0x03 @ SYS_WRITEC + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr + .align 2 +1: .word _GLOBAL_OFFSET_TABLE_ - . + .word semi_writec_buf(GOT) +ENDPROC(putc) + + .bss + .global semi_writec_buf + .type semi_writec_buf, %object +semi_writec_buf: + .space 4 + .size semi_writec_buf, 4 + +#endif -- cgit v1.2.3 From 92bdd3f5eba299b33c2f4407977d6fa2e2a6a0da Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 31 May 2013 22:49:22 +0100 Subject: ARM: 7742/1: topology: export cpu_topology The cpu_topology symbol is required by any driver using the topology interfaces, which leads to a couple of build errors: ERROR: "cpu_topology" [drivers/net/ethernet/sfc/sfc.ko] undefined! ERROR: "cpu_topology" [drivers/cpufreq/arm_big_little.ko] undefined! ERROR: "cpu_topology" [drivers/block/mtip32xx/mtip32xx.ko] undefined! The obvious solution is to export this symbol. Signed-off-by: Arnd Bergmann Acked-by: Will Deacon Cc: stable@vger.kernel.org Cc: Nicolas Pitre Cc: Vincent Guittot Signed-off-by: Russell King --- arch/arm/kernel/topology.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index f10316b4ecdc..c5a59546a256 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {} * cpu topology table */ struct cputopo_arm cpu_topology[NR_CPUS]; +EXPORT_SYMBOL_GPL(cpu_topology); const struct cpumask *cpu_coregroup_mask(int cpu) { -- cgit v1.2.3 From da94a829305f1c217cfdf6771cb1faca0917e3b9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 31 May 2013 22:50:47 +0100 Subject: ARM: 7743/1: compressed/head.S: work around new binutils warning In August 2012, Matthew Gretton-Dann checked a change into binutils labelled "Error on obsolete & warn on deprecated registers", apparently as part of ARMv8 support. Apparently, this was supposed to emit the message "Warning: This coprocessor register access is deprecated in ARMv8" when using certain mcr/mrc instructions and building for ARMv8. Unfortunately, the message that is actually emitted appears to be '(null)', which is less helpful in comparison. Even more unfortunately, this is biting us on every single kernel build with a new gas, because arch/arm/boot/compressed/head.S and some other files in that directory are built with -march=all since kernel commit 80cec14a8 "[ARM] Add -march=all to assembly file build in arch/arm/boot/compressed" back in v2.6.28. This patch reverts Russell's nice solution and instead marks the head.S file to be built for armv7-a, which fortunately lets us build all instructions in that file without warnings even on the broken binutils. Without this patch, building anything results in: arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:565: Warning: (null) arch/arm/boot/compressed/head.S:676: Warning: (null) arch/arm/boot/compressed/head.S:698: Warning: (null) arch/arm/boot/compressed/head.S:722: Warning: (null) arch/arm/boot/compressed/head.S:726: Warning: (null) arch/arm/boot/compressed/head.S:957: Warning: (null) arch/arm/boot/compressed/head.S:996: Warning: (null) arch/arm/boot/compressed/head.S:997: Warning: (null) arch/arm/boot/compressed/head.S:1027: Warning: (null) arch/arm/boot/compressed/head.S:1035: Warning: (null) arch/arm/boot/compressed/head.S:1046: Warning: (null) arch/arm/boot/compressed/head.S:1060: Warning: (null) arch/arm/boot/compressed/head.S:1092: Warning: (null) arch/arm/boot/compressed/head.S:1094: Warning: (null) arch/arm/boot/compressed/head.S:1095: Warning: (null) arch/arm/boot/compressed/head.S:1102: Warning: (null) arch/arm/boot/compressed/head.S:1134: Warning: (null) Signed-off-by: Arnd Bergmann Cc: stable@vger.kernel.org Cc: Matthew Gretton-Dann Signed-off-by: Russell King --- arch/arm/boot/compressed/Makefile | 2 +- arch/arm/boot/compressed/head-sa1100.S | 1 + arch/arm/boot/compressed/head-shark.S | 1 + arch/arm/boot/compressed/head.S | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3580d57ea218..79e9bdbfc491 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) -asflags-y := -Wa,-march=all -DZIMAGE +asflags-y := -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S index 6179d94dd5c6..3115e313d9f6 100644 --- a/arch/arm/boot/compressed/head-sa1100.S +++ b/arch/arm/boot/compressed/head-sa1100.S @@ -11,6 +11,7 @@ #include .section ".start", "ax" + .arch armv4 __SA1100_start: diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S index 089c560e07f1..92b56897ed64 100644 --- a/arch/arm/boot/compressed/head-shark.S +++ b/arch/arm/boot/compressed/head-shark.S @@ -18,6 +18,7 @@ .section ".start", "ax" + .arch armv4 b __beginning __ofw_data: .long 0 @ the number of memory blocks diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fe4d9c3ad761..693855995407 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -11,6 +11,7 @@ #include #include + .arch armv7-a /* * Debugging stuff * -- cgit v1.2.3 From ced2a3b84965f1be8b6a142d6029faf241f109af Mon Sep 17 00:00:00 2001 From: Marc C Date: Wed, 5 Jun 2013 22:02:23 +0100 Subject: ARM: 7750/1: update legacy CPU ID in decompressor cache support jump table The previous mask values for the legacy ARM CPU IDs were conflicting with the CPU ID assignments for late-generation CPUs (like the Qualcomm MSM/QSD or Broadcom Brahma-15 processors). This change corrects the legacy ARM CPU ID value so that the jump table can fall-through to the appropriate cache maintenance / MMU functions. Signed-off-by: Marc C Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 693855995407..032a8d987148 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -806,8 +806,8 @@ call_cache_fn: adr r12, proc_types .align 2 .type proc_types,#object proc_types: - .word 0x00000000 @ old ARM ID - .word 0x0000f000 + .word 0x41000000 @ old ARM ID + .word 0xff00f000 mov pc, lr THUMB( nop ) mov pc, lr -- cgit v1.2.3 From 509eb76ebf9771abc9fe51859382df2571f11447 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 5 Jun 2013 11:20:33 +0100 Subject: ARM: 7747/1: pcpu: ensure __my_cpu_offset cannot be re-ordered across barrier() __my_cpu_offset is non-volatile, since we want its value to be cached when we access several per-cpu variables in a row with preemption disabled. This means that we rely on preempt_{en,dis}able to hazard with the operation via the barrier() macro, so that we can't end up migrating CPUs without reloading the per-cpu offset. Unfortunately, GCC doesn't treat a "memory" clobber on a non-volatile asm block as a side-effect, and will happily re-order it before other memory clobbers (including those in prempt_disable()) and cache the value. This has been observed to break the cmpxchg logic in the slub allocator, leading to livelock in kmem_cache_alloc in mainline kernels. This patch adds a dummy memory input operand to __my_cpu_offset, forcing it to be ordered with respect to the barrier() macro. Cc: Cc: Rob Herring Reviewed-by: Nicolas Pitre Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/percpu.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h index 968c0a14e0a3..209e6504922e 100644 --- a/arch/arm/include/asm/percpu.h +++ b/arch/arm/include/asm/percpu.h @@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off) static inline unsigned long __my_cpu_offset(void) { unsigned long off; - /* Read TPIDRPRW */ - asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory"); + register unsigned long *sp asm ("sp"); + + /* + * Read TPIDRPRW. + * We want to allow caching the value, so avoid using volatile and + * instead use a fake stack read to hazard against barrier(). + */ + asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp)); + return off; } #define __my_cpu_offset __my_cpu_offset() -- cgit v1.2.3 From 29eb77825cc7da8d45b642de2de3d423dc8a363f Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 5 Jun 2013 12:26:50 +0200 Subject: arch, mm: Remove tlb_fast_mode() Since the introduction of preemptible mmu_gather TLB fast mode has been broken. TLB fast mode relies on there being absolutely no concurrency; it frees pages first and invalidates TLBs later. However now we can get concurrency and stuff goes *bang*. This patch removes all tlb_fast_mode() code; it was found the better option vs trying to patch the hole by entangling tlb invalidation with the scheduler. Cc: Thomas Gleixner Cc: Russell King Cc: Tony Luck Reported-by: Max Filippov Signed-off-by: Peter Zijlstra Signed-off-by: Linus Torvalds --- arch/arm/include/asm/tlb.h | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 99a19512ee26..bdf2b8458ec1 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -33,18 +33,6 @@ #include #include -/* - * We need to delay page freeing for SMP as other CPUs can access pages - * which have been removed but not yet had their TLB entries invalidated. - * Also, as ARMv7 speculative prefetch can drag new entries into the TLB, - * we need to apply this same delaying tactic to ensure correct operation. - */ -#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7) -#define tlb_fast_mode(tlb) 0 -#else -#define tlb_fast_mode(tlb) 1 -#endif - #define MMU_GATHER_BUNDLE 8 /* @@ -112,12 +100,10 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb) static inline void tlb_flush_mmu(struct mmu_gather *tlb) { tlb_flush(tlb); - if (!tlb_fast_mode(tlb)) { - free_pages_and_swap_cache(tlb->pages, tlb->nr); - tlb->nr = 0; - if (tlb->pages == tlb->local) - __tlb_alloc_page(tlb); - } + free_pages_and_swap_cache(tlb->pages, tlb->nr); + tlb->nr = 0; + if (tlb->pages == tlb->local) + __tlb_alloc_page(tlb); } static inline void @@ -178,11 +164,6 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { - if (tlb_fast_mode(tlb)) { - free_page_and_swap_cache(page); - return 1; /* avoid calling tlb_flush_mmu */ - } - tlb->pages[tlb->nr++] = page; VM_BUG_ON(tlb->nr > tlb->max); return tlb->max - tlb->nr; -- cgit v1.2.3 From a93d8a1cea0899982993e9a93404c6f78b123697 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Francois Date: Thu, 6 Jun 2013 08:48:07 -0600 Subject: ARM: omap3: clock: fix wrong container_of in clock36xx.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock have parent defined as clk_divider. Fix the function to use clk_divider. Tested with 3.9 on dm3730. Signed-off-by: Jean-Philippe François Cc: NeilBrown Cc: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock36xx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 8f3bf4e50908..bbd6a3f717e6 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -20,11 +20,12 @@ #include #include +#include #include #include "clock.h" #include "clock36xx.h" - +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) /** * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering @@ -39,29 +40,28 @@ */ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { - struct clk_hw_omap *parent; + struct clk_divider *parent; struct clk_hw *parent_hw; - u32 dummy_v, orig_v, clksel_shift; + u32 dummy_v, orig_v; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); - parent = to_clk_hw_omap(parent_hw); + parent = to_clk_divider(parent_hw); /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(parent->clksel_mask); - orig_v = __raw_readl(parent->clksel_reg); + orig_v = __raw_readl(parent->reg); dummy_v = orig_v; /* Write any other value different from the Read value */ - dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, parent->clksel_reg); + dummy_v ^= (1 << parent->shift); + __raw_writel(dummy_v, parent->reg); /* Write the original divider */ - __raw_writel(orig_v, parent->clksel_reg); + __raw_writel(orig_v, parent->reg); } return ret; -- cgit v1.2.3 From 4089fe95bfed295c8ad38251d5fe02b6b0ba684c Mon Sep 17 00:00:00 2001 From: Nicolas Schichan Date: Thu, 6 Jun 2013 19:00:46 +0200 Subject: ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant(). MPP_F6281_MASK would be previously be returned when on mv88f6282, which would disallow some valid MPP configurations. Commit 830f8b91 (arm: plat-orion: fix printing of "MPP config unavailable on this hardware") made this problem visible as an invalid MPP configuration is now correctly detected and not applied. Signed-off-by: Nicolas Schichan Cc: # v3.9.x Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/mpp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 827cde42414f..e96fd71abd76 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void) kirkwood_pcie_id(&dev, &rev); - if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || - (dev == MV88F6282_DEV_ID)) + if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) return MPP_F6281_MASK; + if (dev == MV88F6282_DEV_ID) + return MPP_F6282_MASK; if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) return MPP_F6192_MASK; if (dev == MV88F6180_DEV_ID) -- cgit v1.2.3 From 5f1f3d5088316f827591764aa6a5e7161eb514bd Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 6 Jun 2013 11:21:23 +0200 Subject: arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-gp.dts | 5 +++-- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 3ee63d128e27..76db557adbe7 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -39,8 +39,9 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 - 0xf0000000 0 0xf0000000 0x1000000>; + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; internal-regs { serial@12000 { diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 46b785064dd8..fdea75c73411 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,8 +27,9 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 - 0xf0000000 0 0xf0000000 0x8000000>; + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; internal-regs { serial@12000 { -- cgit v1.2.3 From 437d8ac510b90610da814ae25a7b79aaf3b4910f Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 4 Jun 2013 09:49:10 +0530 Subject: ARM: EXYNOS: uncompress - print debug messages if DEBUG_LL is defined Printing low-level debug messages make an assumption that the specified UART port has been preconfigured by the bootloader. Incorrectly specified UART port results in system getting stalled while printing the message "Uncompressing Linux... done, booting the kernel" This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since the UART port might different for different board, it is not possible to specify it correctly for every board that use a common defconfig file. Calling this print subroutine only when DEBUG_LL fixes the problem. By disabling DEBUG_LL in default config file, we would be able to boot multiple boards with different default UART ports. With this current approach, we miss the print "Uncompressing Linux... done, booting the kernel." when DEBUG_LL is not defined. Signed-off-by: Tushar Behera Signed-off-by: Olof Johansson --- arch/arm/plat-samsung/include/plat/uncompress.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 438b24846e7f..02b66d723d1a 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -66,6 +66,9 @@ uart_rd(unsigned int reg) static void putc(int ch) { + if (!config_enabled(CONFIG_DEBUG_LL)) + return; + if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { int level; @@ -118,7 +121,12 @@ static void arch_decomp_error(const char *x) #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO static inline void arch_enable_uart_fifo(void) { - u32 fifocon = uart_rd(S3C2410_UFCON); + u32 fifocon; + + if (!config_enabled(CONFIG_DEBUG_LL)) + return; + + fifocon = uart_rd(S3C2410_UFCON); if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { fifocon |= S3C2410_UFCON_RESETBOTH; -- cgit v1.2.3 From 9c1fcdccc7ce5611ec1edf45dbbe51b10e333bd3 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 5 Jun 2013 13:56:33 -0700 Subject: ARM: exynos: add debug_ll_io_init() call in exynos_init_io() If the early MMU mapping of the UART happens to get booted out of the TLB between the start of paging_init() and when we finally re-add the UART at the very end of s3c_init_cpu(), we'll get a hang at bootup if we've got early_printk enabled. Avoid this hang by calling debug_ll_io_init() early. Without this patch, you can reliably reproduce a hang when early printk is enabled by adding flush_tlb_all() at the start of exynos_init_io(). After this patch the hang goes away. Signed-off-by: Doug Anderson Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/mach-exynos/common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 027c9e7f0d13..f7e504b7874d 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -386,6 +386,8 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, void __init exynos_init_io(struct map_desc *mach_desc, int size) { + debug_ll_io_init(); + #ifdef CONFIG_OF if (initial_boot_params) of_scan_flat_dt(exynos_fdt_map_chipid, NULL); -- cgit v1.2.3 From 7e5955db458b2d349a8180242afebc78a13ed023 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 7 Jun 2013 11:17:07 +0800 Subject: ARM: prima2: fix incorrect panic usage In prima2, some functions of checking DT is registered in initcall level. If it doesn't match the compatible name of sirf, kernel will panic. It blocks the usage of multiplatform on other verndor. The error message is in below. Knic - not syncing: unable to find compatible pwrc node in dtb CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc3-00006-gd7f26ea-dirty #86 [] (unwind_backtrace+0x0/0xf8) from [] (show_stack+0x10/0x1) [] (show_stack+0x10/0x14) from [] (panic+0x90/0x1e8) [] (panic+0x90/0x1e8) from [] (sirfsoc_of_pwrc_init+0x24/0x) [] (sirfsoc_of_pwrc_init+0x24/0x58) from [] (do_one_initcal) [] (do_one_initcall+0x90/0x150) from [] (kernel_init_freeab) [] (kernel_init_freeable+0xfc/0x1c4) from [] (kernel_init+0) [] (kernel_init+0x8/0xe4) from [] (ret_from_fork+0x14/0x3c) Signen-off-by: Haojian Zhuang Signed-off-by: Olof Johansson --- arch/arm/mach-prima2/pm.c | 6 ++++-- arch/arm/mach-prima2/rstc.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index 9936c180bf01..8f595c0cc8d9 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void) struct device_node *np; np = of_find_matching_node(NULL, pwrc_ids); - if (!np) - panic("unable to find compatible pwrc node in dtb\n"); + if (!np) { + pr_err("unable to find compatible sirf pwrc node in dtb\n"); + return -ENOENT; + } /* * pwrc behind rtciobrg is not located in memory space diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c index 435019ca0a48..d5e0cbc934c0 100644 --- a/arch/arm/mach-prima2/rstc.c +++ b/arch/arm/mach-prima2/rstc.c @@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void) struct device_node *np; np = of_find_matching_node(NULL, rstc_ids); - if (!np) - panic("unable to find compatible rstc node in dtb\n"); + if (!np) { + pr_err("unable to find compatible sirf rstc node in dtb\n"); + return -ENOENT; + } sirfsoc_rstc_base = of_iomap(np, 0); if (!sirfsoc_rstc_base) -- cgit v1.2.3 From cd3fc1b9a34e535a8acbead7461475fbc43bdd49 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 17 May 2013 18:24:29 +0200 Subject: ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platforms This patch makes legacy code on suspend/resume path being executed conditionally, on non-DT platforms only, to fix suspend/resume of DT-enabled systems, for which the code is inappropriate. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park [olof: add #include ] Signed-off-by: Olof Johansson --- arch/arm/plat-samsung/pm.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 53210ec4e8ec..bd7124c87fea 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -261,7 +262,8 @@ static int s3c_pm_enter(suspend_state_t state) * require a full power-cycle) */ - if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && + if (!of_have_populated_dt() && + !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { printk(KERN_ERR "%s: No wake-up sources!\n", __func__); printk(KERN_ERR "%s: Aborting sleep\n", __func__); @@ -270,8 +272,11 @@ static int s3c_pm_enter(suspend_state_t state) /* save all necessary core registers not covered by the drivers */ - samsung_pm_save_gpios(); - samsung_pm_saved_gpios(); + if (!of_have_populated_dt()) { + samsung_pm_save_gpios(); + samsung_pm_saved_gpios(); + } + s3c_pm_save_uarts(); s3c_pm_save_core(); @@ -310,8 +315,11 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_restore_core(); s3c_pm_restore_uarts(); - samsung_pm_restore_gpios(); - s3c_pm_restored_gpios(); + + if (!of_have_populated_dt()) { + samsung_pm_restore_gpios(); + s3c_pm_restored_gpios(); + } s3c_pm_debug_init(); -- cgit v1.2.3 From 691557941af4c12bd307ad81a4d9fa9c7743ac28 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Fri, 7 Jun 2013 10:35:35 +0100 Subject: ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrect On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR register returns zero when it should return one. This leads to cache maintenance operations which rely on this value to not function as intended, causing data corruption. The workaround for this errata is to detect affected CPUs and correct the LoUIS value read. Acked-by: Will Deacon Acked-by: Nicolas Pitre Cc: stable@vger.kernel.org Signed-off-by: Jon Medhurst Signed-off-by: Russell King --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/mm/cache-v7.S | 8 ++++++++ 2 files changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49d993cee512..239fa96c12bb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1189,6 +1189,16 @@ config PL310_ERRATA_588369 is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations. +config ARM_ERRATA_643719 + bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 643719 Cortex-A9 (prior to + r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR + register returns zero when it should return one. The workaround + corrects this value, ensuring cache maintenance operations which use + it behave as intended and avoiding data corruption. + config ARM_ERRATA_720789 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" depends on CPU_V7 diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 15451ee4acc8..515b00064da8 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -92,6 +92,14 @@ ENTRY(v7_flush_dcache_louis) mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr +#ifdef CONFIG_ARM_ERRATA_643719 + ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register + ALT_UP(moveq pc, lr) @ LoUU is zero, so nothing to do + ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? + biceq r2, r2, #0x0000000f @ clear minor revision number + teqeq r2, r1 @ test for errata affected core and if so... + orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') +#endif ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 -- cgit v1.2.3 From 37468b30a3948bbbdf9d664678f611510d987e65 Mon Sep 17 00:00:00 2001 From: Po-Yu Chuang Date: Fri, 7 Jun 2013 12:15:45 +0100 Subject: ARM: 7753/1: map_init_section flushes incorrect pmd This bug was introduced in commit e651eab0. Some v4/v5 platforms failed to boot due to this. Signed-off-by: Po-Yu Chuang Signed-off-by: Russell King --- arch/arm/mm/mmu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e0d8565671a6..4d409e6a552d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -616,10 +616,12 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, } while (pte++, addr += PAGE_SIZE, addr != end); } -static void __init map_init_section(pmd_t *pmd, unsigned long addr, +static void __init __map_init_section(pmd_t *pmd, unsigned long addr, unsigned long end, phys_addr_t phys, const struct mem_type *type) { + pmd_t *p = pmd; + #ifndef CONFIG_ARM_LPAE /* * In classic MMU format, puds and pmds are folded in to @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr, phys += SECTION_SIZE; } while (pmd++, addr += SECTION_SIZE, addr != end); - flush_pmd_entry(pmd); + flush_pmd_entry(p); } static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, @@ -661,7 +663,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, */ if (type->prot_sect && ((addr | next | phys) & ~SECTION_MASK) == 0) { - map_init_section(pmd, addr, next, phys, type); + __map_init_section(pmd, addr, next, phys, type); } else { alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys), type); -- cgit v1.2.3 From 049be07053ebbf0ee8543caea23ae7bdf0765bb2 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 10 Jun 2013 18:05:51 +0100 Subject: ARM: 7754/1: Fix the CPU ID and the mask associated to the PJ4B This commit fixes the ID and mask for the PJ4B which was too restrictive and didn't match the CPU of the Armada 370 SoC. Signed-off-by: Gregory CLEMENT Reviewed-by: Will Deacon Cc: Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c73a7301ff7..4c8c9c10a388 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -409,8 +409,8 @@ __v7_ca9mp_proc_info: */ .type __v7_pj4b_proc_info, #object __v7_pj4b_proc_info: - .long 0x562f5840 - .long 0xfffffff0 + .long 0x560f5800 + .long 0xff0fff00 __v7_proc __v7_pj4b_setup .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info -- cgit v1.2.3 From 1bc39742aab09248169ef9d3727c9def3528b3f3 Mon Sep 17 00:00:00 2001 From: Simon Baatz Date: Mon, 10 Jun 2013 21:10:12 +0100 Subject: ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that the pages it needs to handle are kernel mapped only. However, for example when doing direct I/O, pages with user space mappings may occur. Thus, continue to do lazy flushing if there are no user space mappings. Otherwise, flush the kernel cache lines directly. Signed-off-by: Simon Baatz Reviewed-by: Catalin Marinas Cc: # 3.2+ Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 4 +--- arch/arm/mm/flush.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index bff71388e72a..17d0ae8672fa 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -320,9 +320,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma, } #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE -static inline void flush_kernel_dcache_page(struct page *page) -{ -} +extern void flush_kernel_dcache_page(struct page *); #define flush_dcache_mmap_lock(mapping) \ spin_lock_irq(&(mapping)->tree_lock) diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 0d473cce501c..32aa5861119f 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -300,6 +300,39 @@ void flush_dcache_page(struct page *page) } EXPORT_SYMBOL(flush_dcache_page); +/* + * Ensure cache coherency for the kernel mapping of this page. We can + * assume that the page is pinned via kmap. + * + * If the page only exists in the page cache and there are no user + * space mappings, this is a no-op since the page was already marked + * dirty at creation. Otherwise, we need to flush the dirty kernel + * cache lines directly. + */ +void flush_kernel_dcache_page(struct page *page) +{ + if (cache_is_vivt() || cache_is_vipt_aliasing()) { + struct address_space *mapping; + + mapping = page_mapping(page); + + if (!mapping || mapping_mapped(mapping)) { + void *addr; + + addr = page_address(page); + /* + * kmap_atomic() doesn't set the page virtual + * address for highmem pages, and + * kunmap_atomic() takes care of cache + * flushing already. + */ + if (!IS_ENABLED(CONFIG_HIGHMEM) || addr) + __cpuc_flush_dcache_area(addr, PAGE_SIZE); + } + } +} +EXPORT_SYMBOL(flush_kernel_dcache_page); + /* * Flush an anonymous page so that users of get_user_pages() * can safely access the data. The expected sequence is: -- cgit v1.2.3 From 69f91ff8c93c778cb65b71d9b2d95ff62956354f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 12 Jun 2013 10:56:43 +0100 Subject: ARM: 7756/1: zImage/virt: remove hyp-stub.S during distclean Make sure hyp-stub.S gets removed during make distclean, this left over file was introduced in commit: 424e599 ARM: zImage/virt: hyp mode entry support for the zImage loader Signed-off-by: Magnus Damm Acked-by: Dave Martin Reviewed-by: Simon Horman Signed-off-by: Russell King --- arch/arm/boot/compressed/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 79e9bdbfc491..120b83bfde20 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -116,7 +116,8 @@ targets := vmlinux vmlinux.lds \ # Make sure files are removed during clean extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \ - lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) + lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \ + hyp-stub.S ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) -- cgit v1.2.3 From 0abb6aeacc20822cd7baee82fd3b61169ca3f32e Mon Sep 17 00:00:00 2001 From: Padmavathi Venna Date: Wed, 12 Jun 2013 13:53:44 +0530 Subject: ARM: dts: Correct the base address of pinctrl_3 on Exynos5250 This patch corrects the base address of pinctrl_3 on Exynos5250 platform. Signed-off-by: Padmavathi Venna Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d1650fb34c0a..ded558bb0f3b 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -763,7 +763,7 @@ }; }; - pinctrl@03680000 { + pinctrl@03860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 0673524238a6..fc9fb3d526e2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -161,9 +161,9 @@ interrupts = <0 50 0>; }; - pinctrl_3: pinctrl@03680000 { + pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5250-pinctrl"; - reg = <0x0368000 0x1000>; + reg = <0x03860000 0x1000>; interrupts = <0 47 0>; }; -- cgit v1.2.3 From 19ab428f4b7988ef3ac727c680efc193ef53ce14 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 14 Jun 2013 16:14:14 +0100 Subject: ARM: 7759/1: decouple CPU offlining from reboot/shutdown Add comments to machine_shutdown()/halt()/power_off()/restart() that describe their purpose and/or requirements re: CPUs being active/not. In machine_shutdown(), replace the call to smp_send_stop() with a call to disable_nonboot_cpus(). This completely disables all but one CPU, thus satisfying the requirement that only a single CPU be active for kexec. Adjust Kconfig dependencies for this change. In machine_halt()/power_off()/restart(), call smp_send_stop() directly, rather than via machine_shutdown(); these functions don't need to completely de-activate all CPUs using hotplug, but rather just quiesce them. Remove smp_kill_cpus(), and its call from smp_send_stop(). smp_kill_cpus() was indirectly calling smp_ops.cpu_kill() without calling smp_ops.cpu_die() on the target CPUs first. At least some implementations of smp_ops had issues with this; it caused cpu_kill() to hang on Tegra, for example. Since smp_send_stop() is only used for shutdown, halt, and power-off, there is no need to attempt any kind of CPU hotplug here. Adjust Kconfig to reflect that machine_shutdown() (and hence kexec) relies upon disable_nonboot_cpus(). However, this alone doesn't guarantee that hotplug will work, or even that hotplug is implemented for a particular piece of HW that a multi-platform zImage runs on. Hence, add error-checking to machine_kexec() to determine whether it did work. Suggested-by: Russell King Signed-off-by: Stephen Warren Acked-by: Will Deacon Tested-by: Zhangfei Gao Signed-off-by: Russell King --- arch/arm/Kconfig | 2 +- arch/arm/kernel/machine_kexec.c | 4 ++++ arch/arm/kernel/process.c | 43 +++++++++++++++++++++++++++++++++++------ arch/arm/kernel/smp.c | 13 ------------- 4 files changed, 42 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 239fa96c12bb..2651b1da1c56 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2016,7 +2016,7 @@ config XIP_PHYS_ADDR config KEXEC bool "Kexec system call (EXPERIMENTAL)" - depends on (!SMP || HOTPLUG_CPU) + depends on (!SMP || PM_SLEEP_SMP) help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 8ef8c9337809..4fb074c446bf 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -134,6 +134,10 @@ void machine_kexec(struct kimage *image) unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; + if (num_online_cpus() > 1) { + pr_err("kexec: error: multiple CPUs still online\n"); + return; + } page_list = image->head & PAGE_MASK; diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 282de4826abb..6e8931ccf13e 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -184,30 +184,61 @@ int __init reboot_setup(char *str) __setup("reboot=", reboot_setup); +/* + * Called by kexec, immediately prior to machine_kexec(). + * + * This must completely disable all secondary CPUs; simply causing those CPUs + * to execute e.g. a RAM-based pin loop is not sufficient. This allows the + * kexec'd kernel to use any and all RAM as it sees fit, without having to + * avoid any code or data used by any SW CPU pin loop. The CPU hotplug + * functionality embodied in disable_nonboot_cpus() to achieve this. + */ void machine_shutdown(void) { -#ifdef CONFIG_SMP - smp_send_stop(); -#endif + disable_nonboot_cpus(); } +/* + * Halting simply requires that the secondary CPUs stop performing any + * activity (executing tasks, handling interrupts). smp_send_stop() + * achieves this. + */ void machine_halt(void) { - machine_shutdown(); + smp_send_stop(); + local_irq_disable(); while (1); } +/* + * Power-off simply requires that the secondary CPUs stop performing any + * activity (executing tasks, handling interrupts). smp_send_stop() + * achieves this. When the system power is turned off, it will take all CPUs + * with it. + */ void machine_power_off(void) { - machine_shutdown(); + smp_send_stop(); + if (pm_power_off) pm_power_off(); } +/* + * Restart requires that the secondary CPUs stop performing any activity + * while the primary CPU resets the system. Systems with a single CPU can + * use soft_restart() as their machine descriptor's .restart hook, since that + * will cause the only available CPU to reset. Systems with multiple CPUs must + * provide a HW restart implementation, to ensure that all CPUs reset at once. + * This is required so that any code running after reset on the primary CPU + * doesn't have to co-ordinate with other CPUs to ensure they aren't still + * executing pre-reset code, and using RAM that the primary CPU's code wishes + * to use. Implementing such co-ordination would be essentially impossible. + */ void machine_restart(char *cmd) { - machine_shutdown(); + smp_send_stop(); arm_pm_restart(reboot_mode, cmd); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 550d63cef68e..5919eb451bb9 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -651,17 +651,6 @@ void smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } -#ifdef CONFIG_HOTPLUG_CPU -static void smp_kill_cpus(cpumask_t *mask) -{ - unsigned int cpu; - for_each_cpu(cpu, mask) - platform_cpu_kill(cpu); -} -#else -static void smp_kill_cpus(cpumask_t *mask) { } -#endif - void smp_send_stop(void) { unsigned long timeout; @@ -679,8 +668,6 @@ void smp_send_stop(void) if (num_online_cpus() > 1) pr_warning("SMP: failed to stop secondary CPUs\n"); - - smp_kill_cpus(&mask); } /* -- cgit v1.2.3 From 8182a34d85698d2fb696bfdafa21140916fd5d47 Mon Sep 17 00:00:00 2001 From: Jonas Jensen Date: Tue, 18 Jun 2013 09:20:50 +0100 Subject: ARM: 7760/1: cpu_fa526_do_idle: remove WFI As it was already suggested by Russell King and Arnd Bergmann: https://lkml.org/lkml/2013/5/16/133 moxart and gemini seem to be the only platforms using CPU_FA526, and instead of pointing arm_pm_idle to an empty function from platform code, it makes sense to remove WFI code from the processor specific idle function. Applies to arm-soc/for-next (and 3.10-rc1). Changes since v1: 1. remove WFI but make sure cpu_fa526_do_idle do not fall through to cpu_fa526_dcache_clean_area Note: moxart boots and prints to UART without this patch, but input is broken. Signed-off-by: Jonas Jensen Signed-off-by: Russell King --- arch/arm/mm/proc-fa526.S | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index d217e9795d74..aaeb6c127c7a 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -81,7 +81,6 @@ ENDPROC(cpu_fa526_reset) */ .align 4 ENTRY(cpu_fa526_do_idle) - mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mov pc, lr -- cgit v1.2.3 From 1ba9bf0a9ae779c1a2b3eb64951e4161d9bad7a9 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Wed, 19 Jun 2013 10:36:26 +0100 Subject: ARM: 7762/1: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes The introduction of the cpu-map topology node in the cpus node implies that cpus node might have children that are not cpu nodes. The DT parsing code needs updating otherwise it would check for cpu nodes properties in nodes that are not required to contain them, resulting in warnings that have no bearing on bindings defined in the dts source file. Cc: [3.8+] Signed-off-by: Lorenzo Pieralisi Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/devtree.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 5af04f6daa33..904cad5ec657 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void) for_each_child_of_node(cpus, cpu) { u32 hwid; + if (of_node_cmp(cpu->type, "cpu")) + continue; + pr_debug(" * %s...\n", cpu->full_name); /* * A device tree containing CPU nodes with missing "reg" -- cgit v1.2.3 From 18d7f152df31e5a326301fdaad385e40874dff80 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Wed, 19 Jun 2013 10:40:48 +0100 Subject: ARM: 7763/1: kernel: fix __cpu_logical_map default initialization The __cpu_logical_map array is statically initialized to 0, which is a valid MPIDR value. To prevent issues with the current implementation, this patch defines an MPIDR_INVALID value, and statically initializes the __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps() tmp_map array used to stash DT reg properties while parsing DT are initialized with the MPIDR_INVALID value as well for consistency. Signed-off-by: Lorenzo Pieralisi Acked-by: Nicolas Pitre Cc: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/cputype.h | 2 ++ arch/arm/include/asm/smp_plat.h | 2 +- arch/arm/kernel/devtree.c | 2 +- arch/arm/kernel/setup.c | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 7652712d1d14..dba62cb1ad08 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -32,6 +32,8 @@ #define MPIDR_HWID_BITMASK 0xFFFFFF +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK) + #define MPIDR_LEVEL_BITS 8 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index aaa61b6f50ff..e78983202737 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void) /* * Logical CPU mapping. */ -extern int __cpu_logical_map[]; +extern u32 __cpu_logical_map[]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] /* * Retrieve logical cpu index corresponding to a given MPIDR[23:0] diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 904cad5ec657..0905502bee15 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void) u32 i, j, cpuidx = 1; u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX }; + u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; bool bootcpu_valid = false; cpus = of_find_node_by_path("/cpus"); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1522c7ae31b0..b4b1d397592b 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -444,7 +444,7 @@ void notrace cpu_init(void) : "r14"); } -int __cpu_logical_map[NR_CPUS]; +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; void __init smp_setup_processor_id(void) { -- cgit v1.2.3 From 63384fd0b1509acf522a8a8fcede09087eedb7df Mon Sep 17 00:00:00 2001 From: Simon Baatz Date: Sat, 22 Jun 2013 22:01:25 +0100 Subject: ARM: 7772/1: Fix missing flush_kernel_dcache_page() for noMMU Commit 1bc3974 (ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page) moved the implementation of flush_kernel_dcache_page() into mm/flush.c but did not implement it on noMMU ARM. Signed-off-by: Simon Baatz Acked-by: Kevin Hilman Cc: # 3.2+: 1bc3974: ARM: 7755/1 Signed-off-by: Russell King --- arch/arm/mm/nommu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index d51225f90ae2..eb5293a69a84 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -57,6 +57,12 @@ void flush_dcache_page(struct page *page) } EXPORT_SYMBOL(flush_dcache_page); +void flush_kernel_dcache_page(struct page *page) +{ + __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); +} +EXPORT_SYMBOL(flush_kernel_dcache_page); + void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long uaddr, void *dst, const void *src, unsigned long len) -- cgit v1.2.3 From 3e0a07f8c401bb43e0f964c5f1285b2cb2028645 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Sun, 23 Jun 2013 10:17:11 +0100 Subject: ARM: 7773/1: PJ4B: Add support for errata 4742 This commit fixes the regression on Armada 370 (the kernal hang during boot) introduced by the commit: "ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead". When coming out of either a Wait for Interrupt (WFI) or a Wait for Event (WFE) IDLE states, a specific timing sensitivity exists between the retiring WFI/WFE instructions and the newly issued subsequent instructions. This sensitivity can result in a CPU hang scenario. The workaround is to insert either a Data Synchronization Barrier (DSB) or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction. This commit was based on the work of Lior Amsalem, but heavily modified to apply the errata fix dynamically according to the processor type thanks to the suggestions of Russell King and Nicolas Pitre. Signed-off-by: Gregory CLEMENT Reviewed-by: Will Deacon Acked-by: Nicolas Pitre Tested-by: Willy Tarreau Cc: Signed-off-by: Russell King --- arch/arm/Kconfig | 14 ++++++++++++++ arch/arm/include/asm/glue-proc.h | 9 +++++++++ arch/arm/mm/proc-macros.S | 5 +++++ arch/arm/mm/proc-v7.S | 34 +++++++++++++++++++++++++++++++--- 4 files changed, 59 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2651b1da1c56..136f263ed47b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1087,6 +1087,20 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config PJ4B_ERRATA_4742 + bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" + depends on CPU_PJ4B && MACH_ARMADA_370 + default y + help + When coming out of either a Wait for Interrupt (WFI) or a Wait for + Event (WFE) IDLE states, a specific timing sensitivity exists between + the retiring WFI/WFE instructions and the newly issued subsequent + instructions. This sensitivity can result in a CPU hang scenario. + Workaround: + The software must insert either a Data Synchronization Barrier (DSB) + or Data Memory Barrier (DMB) command immediately after the WFI/WFE + instruction + config ARM_ERRATA_326103 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" depends on CPU_V6 diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h index ac1dd54724b6..8017e94acc5e 100644 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -230,6 +230,15 @@ # endif #endif +#ifdef CONFIG_CPU_PJ4B +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_pj4b +# endif +#endif + #ifndef MULTI_CPU #define cpu_proc_init __glue(CPU_NAME,_proc_init) #define cpu_proc_fin __glue(CPU_NAME,_proc_fin) diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index f9a0aa725ea9..e3c48a3fe063 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -333,3 +333,8 @@ ENTRY(\name\()_tlb_fns) .endif .size \name\()_tlb_fns, . - \name\()_tlb_fns .endm + +.macro globl_equ x, y + .globl \x + .equ \x, \y +.endm diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 4c8c9c10a388..e35fec34453e 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -138,6 +138,29 @@ ENTRY(cpu_v7_do_resume) mov r0, r8 @ control register b cpu_resume_mmu ENDPROC(cpu_v7_do_resume) +#endif + +#ifdef CONFIG_CPU_PJ4B + globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm + globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init + globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin + globl_equ cpu_pj4b_reset, cpu_v7_reset +#ifdef CONFIG_PJ4B_ERRATA_4742 +ENTRY(cpu_pj4b_do_idle) + dsb @ WFI may enter a low-power mode + wfi + dsb @barrier + mov pc, lr +ENDPROC(cpu_pj4b_do_idle) +#else + globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle +#endif + globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend + globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume + globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + #endif __CPUINIT @@ -350,6 +373,9 @@ __v7_setup_stack: @ define struct processor (see and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 +#ifdef CONFIG_CPU_PJ4B + define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 +#endif .section ".rodata" @@ -362,7 +388,7 @@ __v7_setup_stack: /* * Standard v7 proc info content */ -.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 +.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ @@ -375,7 +401,7 @@ __v7_setup_stack: .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ HWCAP_EDSP | HWCAP_TLS | \hwcaps .long cpu_v7_name - .long v7_processor_functions + .long \proc_fns .long v7wbi_tlb_fns .long v6_user_fns .long v7_cache_fns @@ -407,12 +433,14 @@ __v7_ca9mp_proc_info: /* * Marvell PJ4B processor. */ +#ifdef CONFIG_CPU_PJ4B .type __v7_pj4b_proc_info, #object __v7_pj4b_proc_info: .long 0x560f5800 .long 0xff0fff00 - __v7_proc __v7_pj4b_setup + __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info +#endif /* * ARM Ltd. Cortex A7 processor. -- cgit v1.2.3 From 8d5bc1a6ac40885078bbb0552b4283a3e58c462e Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Sat, 29 Jun 2013 16:25:14 -0700 Subject: ARM: dt: Only print warning, not WARN() on bad cpu map in device tree Due to recent changes and expecations of proper cpu bindings, there are now cases for many of the in-tree devicetrees where a WARN() will hit on boot due to badly formatted /cpus nodes. Downgrade this to a pr_warn() to be less alarmist, since it's not a new problem. Tested on Arndale, Cubox, Seaboard and Panda ES. Panda hits the WARN without this, the others do not. Acked-by: Russell King Signed-off-by: Olof Johansson Signed-off-by: Linus Torvalds --- arch/arm/kernel/devtree.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 0905502bee15..5859c8bc727c 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -152,9 +152,10 @@ void __init arm_dt_init_cpu_maps(void) tmp_map[i] = hwid; } - if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], " - "fall back to default cpu_logical_map\n")) + if (!bootcpu_valid) { + pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); return; + } /* * Since the boot CPU node contains proper data, and all nodes have -- cgit v1.2.3