From 176a1b3dadf08835b9435bed4957daa066702a39 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 19 Mar 2015 21:14:40 +0100 Subject: ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler flags are for ARMv6, and results in: arch/arm/mach-at91/pm_suspend.S:144: Error: selected processor does not support ARM mode `dsb' Enforce ARMv7 flags for pm_suspend.o when CPU_V7 is selected. Reported-by: kbuild test robot Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index ea54c9824d89..12440ec60924 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -15,6 +15,9 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm_suspend.o +ifeq ($(CONFIG_CPU_V7),y) +AFLAGS_pm_suspend.o := -march=armv7-a +endif ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG endif -- cgit v1.2.3 From a18d0699dd18ba5661c321ebd67e6056656b6765 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Mar 2015 23:44:37 +0100 Subject: ARM: at91/pm: move the standby functions to pm.c The standby functions are now only used in pm.c, move them there. Also, they are not inlined as a pointer to those functions is passed to the cpuidle driver. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/pm.h | 92 ------------------------------------------------- 2 files changed, 89 insertions(+), 92 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index ac947cdd506c..0a71c69618f8 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -216,6 +216,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void)) at91_cpuidle_device.dev.platform_data = at91_standby; } +/* + * The AT91RM9200 goes into self-refresh mode with this command, and will + * terminate self-refresh automatically on the next SDRAM access. + * + * Self-refresh mode is exited as soon as a memory access is made, but we don't + * know for sure when that happens. However, we need to restore the low-power + * mode if it was enabled before going idle. Restoring low-power mode while + * still in self-refresh is "not recommended", but seems to work. + */ +static void at91rm9200_standby(void) +{ + u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); + + asm volatile( + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, %0, c7, c10, 4\n\t" + " str %0, [%1, %2]\n\t" + " str %3, [%1, %4]\n\t" + " mcr p15, 0, %0, c7, c0, 4\n\t" + " str %5, [%1, %2]" + : + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), + "r" (1), "r" (AT91RM9200_SDRAMC_SRR), + "r" (lpr)); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91_ddr_standby(void) +{ + /* Those two values allow us to delay self-refresh activation + * to the maximum. */ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + } + + saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); + lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; + lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91sam9_sdram_standby(void) +{ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + } + + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); +} + static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index dcacfa1ad3fa..3223967d3460 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -23,96 +23,4 @@ #define AT91_PM_SLOW_CLOCK 0x01 -/* - * The AT91RM9200 goes into self-refresh mode with this command, and will - * terminate self-refresh automatically on the next SDRAM access. - * - * Self-refresh mode is exited as soon as a memory access is made, but we don't - * know for sure when that happens. However, we need to restore the low-power - * mode if it was enabled before going idle. Restoring low-power mode while - * still in self-refresh is "not recommended", but seems to work. - */ - -#ifndef __ASSEMBLY__ -static inline void at91rm9200_standby(void) -{ - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); - - asm volatile( - "b 1f\n\t" - ".align 5\n\t" - "1: mcr p15, 0, %0, c7, c10, 4\n\t" - " str %0, [%1, %2]\n\t" - " str %3, [%1, %4]\n\t" - " mcr p15, 0, %0, c7, c0, 4\n\t" - " str %5, [%1, %2]" - : - : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), - "r" (1), "r" (AT91RM9200_SDRAMC_SRR), - "r" (lpr)); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91_ddr_standby(void) -{ - /* Those two values allow us to delay self-refresh activation - * to the maximum. */ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); - lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; - lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); - - cpu_do_idle(); - - at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91sam9_sdram_standby(void) -{ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); - lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; - lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); - lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; - lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); - - cpu_do_idle(); - - at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); -} - -#endif #endif -- cgit v1.2.3 From 2e57dc087c27b8b0bd4a9e5f2c6f28f3cd0b47ff Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Mar 2015 23:44:38 +0100 Subject: ARM: at91/pm: move AT91_MEMCTRL_* to pm.h the AT91_MEMCTRL_* defines are only used by the pm code, move them to pm.h Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/include/mach/at91_ramc.h | 4 ---- arch/arm/mach-at91/pm.h | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h index e4492b151fee..493bc486e858 100644 --- a/arch/arm/mach-at91/include/mach/at91_ramc.h +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h @@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[]; .extern at91_ramc_base #endif -#define AT91_MEMCTRL_MC 0 -#define AT91_MEMCTRL_SDRAMC 1 -#define AT91_MEMCTRL_DDRSDR 2 - #include #include #include diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 3223967d3460..ecd875a91d52 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -15,6 +15,10 @@ #include +#define AT91_MEMCTRL_MC 0 +#define AT91_MEMCTRL_SDRAMC 1 +#define AT91_MEMCTRL_DDRSDR 2 + #define AT91_PM_MEMTYPE_MASK 0x0f #define AT91_PM_MODE_OFFSET 4 -- cgit v1.2.3