From b2dc0a08845af9d6ea990a1a28d4545998707570 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 20 Jun 2009 15:36:09 -0400 Subject: Blackfin: drop dead flash_probe call There are no CONFIG_{BLK,CHR}_DEV_FLASH Kconfig options, and there is no flash_probe() function, so not really sure what this code is all about. Seems to be dead code that stretches way back to the start of the Blackfin port. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 6136c33e919f..6e150d9b8862 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -868,13 +868,6 @@ void __init setup_arch(char **cmdline_p) else printk(KERN_CONT "and Disabled\n"); -#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) - /* we need to initialize the Flashrom device here since we might - * do things with flash early on in the boot - */ - flash_probe(); -#endif - printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); /* Newer parts mirror SWRST bits in SYSCR */ -- cgit v1.2.3 From 0e4edcf0b0f7d96c4be7788b13bee82e4d3ba0ce Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 22 Jun 2009 20:23:48 +0000 Subject: Blackfin: work around anomaly 05000281 Add missing anomaly workaround for anomaly 05000281 - we can't return to instructions which cause hardware errors otherwise we trigger the error again which means we go into an infinite loop of handling, returning, and retriggering. This work around confuses gdb when the error occurs as the PC will seemed to have moved, so a better long term fix will need to be figured out, but for now this is better than an infinite crash loop. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/traps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 8a1caf2bb5b9..664de56296cb 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -619,7 +619,8 @@ asmlinkage void trap_c(struct pt_regs *fp) force_sig_info(sig, &info, current); } - if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) + if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) || + (ANOMALY_05000281 && trapnr == VEC_HWERR)) fp->pc = SAFE_USER_INSTRUCTION; traps_done: -- cgit v1.2.3 From 15627bd35c6f02d159e0cb41d287dcba3a23a135 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 23 Jun 2009 11:21:34 +0000 Subject: Blackfin: restore exception banner when dumping crash info Previous unification code put the exception banner behind the "is oops" logic when it should have been printed all the time. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/traps.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 664de56296cb..9efac0f2e2ce 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -570,11 +570,12 @@ asmlinkage void trap_c(struct pt_regs *fp) if (kernel_mode_regs(fp) || (current && !current->mm)) { console_verbose(); oops_in_progress = 1; - if (strerror) - verbose_printk(strerror); } if (sig != SIGTRAP) { + if (strerror) + verbose_printk(strerror); + dump_bfin_process(fp); dump_bfin_mem(fp); show_regs(fp); -- cgit v1.2.3 From dc437b1b596e310bb583de3868c3d61a6798c81c Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 26 Jun 2009 12:23:51 +0000 Subject: Blackfin: fix silent crash when no uClinux MTD filesystem exists Since we need to relocate the attached filesystem with the uClinux MTD map (to handle some anomalies), we need to know its real filesize. If we boot a kernel without a filesystem actually attached, we end up blindly reading and copying garbage (since there is no magic value to detect validity). Often times this results in an early crash and no output. So add a few basic sanity checks before operating on things to catch the majority of cases. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 6e150d9b8862..e4d2da7c1c9d 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -568,17 +568,23 @@ static __init void memory_setup(void) # endif /* ANOMALY_05000263 */ # endif /* CONFIG_ROMFS_FS */ - memory_end -= mtd_size; - - if (mtd_size == 0) { - console_init(); - panic("Don't boot kernel without rootfs attached."); + /* Since the default MTD_UCLINUX has no magic number, we just blindly + * read 8 past the end of the kernel's image, and look at it. + * When no image is attached, mtd_size is set to a random number + * Do some basic sanity checks before operating on things + */ + if (mtd_size == 0 || memory_end <= mtd_size) { + pr_emerg("Could not find valid ram mtd attached.\n"); + } else { + memory_end -= mtd_size; + + /* Relocate MTD image to the top of memory after the uncached memory area */ + uclinux_ram_map.phys = memory_mtd_start = memory_end; + uclinux_ram_map.size = mtd_size; + pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", + _end, mtd_size, (void *)memory_mtd_start); + dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); } - - /* Relocate MTD image to the top of memory after the uncached memory area */ - uclinux_ram_map.phys = memory_mtd_start = memory_end; - uclinux_ram_map.size = mtd_size; - dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); #endif /* CONFIG_MTD_UCLINUX */ #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) -- cgit v1.2.3 From fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 29 Jun 2009 14:20:10 -0400 Subject: Blackfin: handle BF561 Core B memory regions better when SMP=n Rather than assume Core B is always run with caches turned on, let people load into any of the on-chip memory regions. It is their business how the SRAM/Cache regions are utilized, so don't prevent them from being able to load into them. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/process.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 79cad0ac5892..9da36bab7ccb 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -361,7 +361,7 @@ static inline int in_mem_const(unsigned long addr, unsigned long size, unsigned long const_addr, unsigned long const_size) { - return in_mem_const_off(addr, 0, size, const_addr, const_size); + return in_mem_const_off(addr, size, 0, const_addr, const_size); } #define IN_ASYNC(bnum, bctlnum) \ ({ \ @@ -390,13 +390,13 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size) if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; #ifdef COREB_L1_CODE_START - if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; #endif if (in_mem_const(addr, size, L2_START, L2_LENGTH)) @@ -472,13 +472,13 @@ int _access_ok(unsigned long addr, unsigned long size) if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) return 1; #ifdef COREB_L1_CODE_START - if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) return 1; if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) return 1; - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) return 1; - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) return 1; #endif if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) -- cgit v1.2.3 From 532f07ca04c6f8ab0555b00cf5d42dc6f72b802f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 29 Jun 2009 22:45:50 +0000 Subject: Blackfin: fix early_dma_memcpy() handling of busy channels The early logic to locate a free DMA channel and then set it up was broken in a few ways that only manifested itself when we needed to set up more than 2 on chip SRAM regions (most board defaults setup 1 or 2). First, we checked the wrong status register (the destination gets updated, not the source) and second, we did the ssync before rather than after resetting a DMA config register. Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/bfin_dma_5xx.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index e0bf8cc06907..9f9b82816652 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -253,32 +253,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) BUG_ON(src % 4); BUG_ON(size % 4); - /* Force a sync in case a previous config reset on this channel - * occurred. This is needed so subsequent writes to DMA registers - * are not spuriously lost/corrupted. - */ - __builtin_bfin_ssync(); - src_ch = 0; /* Find an avalible memDMA channel */ while (1) { - if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) { - dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; - src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; - } else { + if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; + } else { + dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; + src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; } - if (!bfin_read16(&src_ch->cfg)) { + if (!bfin_read16(&src_ch->cfg)) + break; + else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { + bfin_write16(&src_ch->cfg, 0); break; - } else { - if (bfin_read16(&src_ch->irq_status) & DMA_DONE) - bfin_write16(&src_ch->cfg, 0); } - } + /* Force a sync in case a previous config reset on this channel + * occurred. This is needed so subsequent writes to DMA registers + * are not spuriously lost/corrupted. + */ + __builtin_bfin_ssync(); + /* Destination */ bfin_write32(&dst_ch->start_addr, dst); bfin_write16(&dst_ch->x_count, size >> 2); -- cgit v1.2.3 From 3a920accbb5f88d753ab5a6a47d0dd48b6269f84 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 6 Jul 2009 14:29:08 +0000 Subject: Blackfin: drop duplicate runtime checking of anomaly 05000448 We already catch this anomaly at compile time, and the runtime version is such that it ends up checking on all parts rather than just the ones that might actually have it. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index e4d2da7c1c9d..98c2f79afda3 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -937,10 +937,6 @@ void __init setup_arch(char **cmdline_p) CPU, bfin_revid()); } - /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ - if (bfin_cpuid() == 0x27de && bfin_revid() == 1) - panic("You can't run on this processor due to 05000448"); - printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", -- cgit v1.2.3 From c03c2a87347b849ec927d7d2ea79a6955e19f492 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 8 Jul 2009 12:04:43 +0000 Subject: Blackfin: fix bugs in GPIO resume code Change the bfin_gpio_pm_hibernate_restore() function to: 1) AND restored DATA with DIR (not OR) to get correct final state 2) Restore DATA before setting DIR to avoid glitches Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/bfin_gpio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index beffa00a93c3..6b9446271371 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -686,14 +686,12 @@ void bfin_gpio_pm_hibernate_restore(void) *port_fer[bank] = gpio_bank_saved[bank].fer; #endif gpio_array[bank]->inen = gpio_bank_saved[bank].inen; + gpio_array[bank]->data_set = gpio_bank_saved[bank].data + & gpio_bank_saved[bank].dir; gpio_array[bank]->dir = gpio_bank_saved[bank].dir; gpio_array[bank]->polar = gpio_bank_saved[bank].polar; gpio_array[bank]->edge = gpio_bank_saved[bank].edge; gpio_array[bank]->both = gpio_bank_saved[bank].both; - - gpio_array[bank]->data_set = gpio_bank_saved[bank].data - | gpio_bank_saved[bank].dir; - gpio_array[bank]->maska = gpio_bank_saved[bank].maska; } AWA_DUMMY_READ(maska); -- cgit v1.2.3 From c70c754ff916cedd969a73549799d2167ffefcd6 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 9 Jul 2009 09:58:52 +0000 Subject: Blackfin: drop per-cpu loops_per_jiffy tracking On Blackfin SMP, a per-cpu loops_per_jiffy is pointless since both cores always run at the same CCLK. In addition, the current implementation has flaws since the main consumer for loops_per_jiffy (asm/delay.h) uses the global kernel loops_per_jiffy and not the per_cpu one. So punt all of the per-cpu handling and go back to the global shared one. Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/setup.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 98c2f79afda3..6225edae488e 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -168,7 +168,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu) struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); cpudata->idle = current; - cpudata->loops_per_jiffy = loops_per_jiffy; cpudata->imemctl = bfin_read_IMEM_CONTROL(); cpudata->dmemctl = bfin_read_DMEM_CONTROL(); } @@ -1159,9 +1158,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) sclk/1000000, sclk%1000000); seq_printf(m, "bogomips\t: %lu.%02lu\n" "Calibration\t: %lu loops\n", - (cpudata->loops_per_jiffy * HZ) / 500000, - ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, - (cpudata->loops_per_jiffy * HZ)); + (loops_per_jiffy * HZ) / 500000, + ((loops_per_jiffy * HZ) / 5000) % 100, + (loops_per_jiffy * HZ)); /* Check Cache configutation */ switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { -- cgit v1.2.3 From f574a76a3b19848ac61814756716e26f85f2c3f7 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Thu, 9 Jul 2009 15:11:52 +0000 Subject: Blackfin: work around anomaly 05000189 Similar to anomaly 05000281 but not as bad, we cannot return to the instruction causing a fault otherwise we'll trigger a second false exception. The system can still recover, but it isn't correct. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/traps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 9efac0f2e2ce..bf2b2d1f8ae5 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -621,7 +621,8 @@ asmlinkage void trap_c(struct pt_regs *fp) } if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) || - (ANOMALY_05000281 && trapnr == VEC_HWERR)) + (ANOMALY_05000281 && trapnr == VEC_HWERR) || + (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL))) fp->pc = SAFE_USER_INSTRUCTION; traps_done: -- cgit v1.2.3 From 5bc6e3cfe6db5f33c60f042a9ba203431f334756 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 10 Jul 2009 11:34:51 +0000 Subject: Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/cplb-nompu/cplbinit.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index d6c067782e63..685f160a5a36 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) } /* Cover L1 memory. One 4M area for code and data each is enough. */ - if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { - d_tbl[i_d].addr = L1_DATA_A_START; - d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + if (cpu == 0) { + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { + d_tbl[i_d].addr = L1_DATA_A_START; + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + } + i_tbl[i_i].addr = L1_CODE_START; + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; } - i_tbl[i_i].addr = L1_CODE_START; - i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; - +#ifdef CONFIG_SMP + else { + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { + d_tbl[i_d].addr = COREB_L1_DATA_A_START; + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + } + i_tbl[i_i].addr = COREB_L1_CODE_START; + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; + } +#endif first_switched_dcplb = i_d; first_switched_icplb = i_i; -- cgit v1.2.3