From 3343c1d4482b27a444e76bf53d16df4a6f30b873 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 9 Oct 2008 11:11:11 +0800 Subject: Blackfin arch: Fix BUG: anomaly_threshold is used with ANOMALY_05000363 Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index ebf592b59aab..993464ee93c3 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h @@ -83,7 +83,7 @@ struct bfin_serial_port { unsigned int rx_dma_channel; struct work_struct tx_dma_workqueue; #else -# if ANOMALY_05000230 +# if ANOMALY_05000363 unsigned int anomaly_threshold; # endif #endif -- cgit v1.2.3 From 0c0497c257c12c9ecb8825490a339bfce8a0532f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 9 Oct 2008 17:32:28 +0800 Subject: Blackfin arch: Move all the silicon rev handling to one place Move all the silicon rev handling to one place (Kconfig) and make sure we warn if you are running on silicon that has not been tested on Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/include/mach/bf533.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h index 12a416931991..949801112303 100644 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ b/arch/blackfin/mach-bf533/include/mach/bf533.h @@ -30,8 +30,6 @@ #ifndef __MACH_BF533_H__ #define __MACH_BF533_H__ -#define SUPPORTED_REVID 2 - #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ -- cgit v1.2.3 From 45138439e171111a93273e9c0008b41ac56d0731 Mon Sep 17 00:00:00 2001 From: Javier Herrero Date: Thu, 9 Oct 2008 18:06:47 +0800 Subject: Blackfin arch: flash memory map and dm9000 resources updating Signed-off-by: Javier Herrero Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/boards/H8606.c | 34 ++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index c66a68f30239..72ac3ac8ef76 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -9,7 +9,7 @@ * Modified: * Copyright 2005 National ICT Australia (NICTA) * Copyright 2004-2006 Analog Devices Inc - * Copyright 2007 HV Sistemas S.L. + * Copyright 2007,2008 HV Sistemas S.L. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -64,18 +64,18 @@ static struct platform_device rtc_device = { static struct resource dm9000_resources[] = { [0] = { .start = 0x20300000, - .end = 0x20300000 + 1, + .end = 0x20300002, .flags = IORESOURCE_MEM, }, [1] = { - .start = 0x20300000 + 4, - .end = 0x20300000 + 5, + .start = 0x20300004, + .end = 0x20300006, .flags = IORESOURCE_MEM, }, [2] = { .start = IRQ_PF10, .end = IRQ_PF10, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH), }, }; @@ -140,18 +140,22 @@ static struct platform_device net2272_bfin_device = { #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition bfin_spi_flash_partitions[] = { { - .name = "bootloader(spi)", - .size = 0x00060000, + .name = "bootloader (spi)", + .size = 0x40000, .offset = 0, .mask_flags = MTD_CAP_ROM }, { - .name = "linux kernel(spi)", - .size = 0x100000, - .offset = 0x60000 + .name = "fpga (spi)", + .size = 0x30000, + .offset = 0x40000 }, { - .name = "file system(spi)", - .size = 0x6a0000, - .offset = 0x00160000, + .name = "linux kernel (spi)", + .size = 0x150000, + .offset = 0x70000 + }, { + .name = "jffs2 root file system (spi)", + .size = 0x640000, + .offset = 0x1c0000, } }; @@ -340,7 +344,7 @@ static struct platform_device bfin_sir_device = { static struct plat_serial8250_port serial8250_platform_data [] = { { - .membase = 0x20200000, + .membase = (void *)0x20200000, .mapbase = 0x20200000, .irq = IRQ_PF8, .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, @@ -348,7 +352,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = { .regshift = 1, .uartclk = 66666667, }, { - .membase = 0x20200010, + .membase = (void *)0x20200010, .mapbase = 0x20200010, .irq = IRQ_PF8, .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, -- cgit v1.2.3 From e482cad241c0b7108cbc94959307a73d19ba17d5 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 10 Oct 2008 18:21:45 +0800 Subject: Blackfin arch: print out error/warning if you are running on the incorrect CPU type Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/include/mach/bf533.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h index 949801112303..dfc8c1ad2d7a 100644 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ b/arch/blackfin/mach-bf533/include/mach/bf533.h @@ -141,19 +141,19 @@ #ifdef CONFIG_BF533 #define CPU "BF533" -#define CPUID 0x027a5000 +#define CPUID 0x27a5 #endif #ifdef CONFIG_BF532 #define CPU "BF532" -#define CPUID 0x0275A000 +#define CPUID 0x275A #endif #ifdef CONFIG_BF531 #define CPU "BF531" -#define CPUID 0x027a5000 +#define CPUID 0x27a5 #endif + #ifndef CPU -#define CPU "UNKNOWN" -#define CPUID 0x0 +#error Unknown CPU type - This kernel doesn't seem to be configured properly #endif #endif /* __MACH_BF533_H__ */ -- cgit v1.2.3 From 4e8086d65bd0a606434a4b16611653387f8c9698 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 10 Oct 2008 21:07:55 +0800 Subject: Blackfin arch: update anomaly headers to match the latest sheet Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/include/mach/anomaly.h | 49 ++++++++++++++----------- 1 file changed, 27 insertions(+), 22 deletions(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 8f7ea112fd3a..f544fc56959a 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -97,11 +97,11 @@ /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -131,7 +131,7 @@ /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) +#define ANOMALY_05000265 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ @@ -141,56 +141,59 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (1) +#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (1) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (1) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (1) +#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) /* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (1) +#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (1) +#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (1) +#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) +#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (1) +#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer */ -#define ANOMALY_05000313 (1) +#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (1) +#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) +#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) /* UART Break Signal Issues */ #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) /* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) - +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -268,5 +271,7 @@ /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000386 (1) #endif -- cgit v1.2.3 From 71de1f8a6365ea65346881e526132563d93696d1 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 13 Oct 2008 11:37:34 +0800 Subject: Blackfin arch: make sure we include the fix for SPORT hysteresis when reprogramming clocks As pointed out by Appalayagari Sreedhar, make sure we include the fix for SPORT hysteresis when reprogramming clocks. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/head.S | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 01b2b7ead5ab..619685b94d90 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -78,6 +78,9 @@ ENTRY(_start_dma_code) r1 = PLL_BYPASS; /* Bypass the PLL? */ r1 = r1 << 8; /* Shift it over */ r0 = r1 | r0; /* add them all together */ +#ifdef ANOMALY_05000265 + r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ +#endif p0.h = hi(PLL_CTL); p0.l = lo(PLL_CTL); /* Load the address */ -- cgit v1.2.3