From c9784ebb23be1e2ef23f537d6df04e0ea0206802 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Fri, 4 Dec 2009 06:56:21 +0000 Subject: Blackfin: flush caches on SMP when one core calls another via IPI Sometimes a SMP system will randomly panic at boot. This is due to caches being out of sync when one core tries to signal the other. So when one core calls another via IPI, flush the data caches. Signed-off-by: Yi Li Signed-off-by: Mike Frysinger --- arch/blackfin/mach-common/smp.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/mach-common/smp.c') diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 369e687582b7..eddb720c718e 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -122,9 +122,17 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) wait = msg->call_struct.wait; cpu_clear(cpu, msg->call_struct.pending); func(info); - if (wait) + if (wait) { +#ifdef __ARCH_SYNC_CORE_DCACHE + /* + * 'wait' usually means synchronization between CPUs. + * Invalidate D cache in case shared data was changed + * by func() to ensure cache coherence. + */ + resync_core_dcache(); +#endif cpu_clear(cpu, msg->call_struct.waitmask); - else + } else kfree(msg); } @@ -219,6 +227,13 @@ int smp_call_function(void (*func)(void *info), void *info, int wait) blackfin_dcache_invalidate_range( (unsigned long)(&msg->call_struct.waitmask), (unsigned long)(&msg->call_struct.waitmask)); +#ifdef __ARCH_SYNC_CORE_DCACHE + /* + * Invalidate D cache in case shared data was changed by + * other processors to ensure cache coherence. + */ + resync_core_dcache(); +#endif kfree(msg); } return 0; @@ -261,6 +276,13 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, blackfin_dcache_invalidate_range( (unsigned long)(&msg->call_struct.waitmask), (unsigned long)(&msg->call_struct.waitmask)); +#ifdef __ARCH_SYNC_CORE_DCACHE + /* + * Invalidate D cache in case shared data was changed by + * other processors to ensure cache coherence. + */ + resync_core_dcache(); +#endif kfree(msg); } return 0; -- cgit v1.2.3 From 0d152c27e336b5fd777da7dd3e814617e7305afd Mon Sep 17 00:00:00 2001 From: Yi Li Date: Mon, 28 Dec 2009 10:21:49 +0000 Subject: Blackfin: SMP: make core timers per-cpu clock events for HRT SMP systems require per-cpu local clock event devices in order to enable HRT support. One a BF561, we can use local core timer for this purpose. Originally, there was one global core-timer clock event device set up for core A. To accomplish this feat, we need to split the gptimer0/core timer logic so that each is a standalone clock event. There is no requirement that we only have one clock event source anyways. Once we have this, we just define per-cpu clock event devices for each local core timer. Signed-off-by: Yi Li Signed-off-by: Mike Frysinger --- arch/blackfin/mach-common/smp.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) (limited to 'arch/blackfin/mach-common/smp.c') diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index eddb720c718e..b343ab3764a1 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -365,9 +365,6 @@ int __cpuinit __cpu_up(unsigned int cpu) static void __cpuinit setup_secondary(unsigned int cpu) { -#if !defined(CONFIG_TICKSOURCE_GPTMR0) - struct irq_desc *timer_desc; -#endif unsigned long ilat; bfin_write_IMASK(0); @@ -382,17 +379,6 @@ static void __cpuinit setup_secondary(unsigned int cpu) bfin_irq_flags |= IMASK_IVG15 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; - -#if defined(CONFIG_TICKSOURCE_GPTMR0) - /* Power down the core timer, just to play safe. */ - bfin_write_TCNTL(0); - - /* system timer0 has been setup by CoreA. */ -#else - timer_desc = irq_desc + IRQ_CORETMR; - setup_core_timer(); - timer_desc->chip->enable(IRQ_CORETMR); -#endif } void __cpuinit secondary_start_kernel(void) @@ -435,6 +421,9 @@ void __cpuinit secondary_start_kernel(void) platform_secondary_init(cpu); + /* setup local core timer */ + bfin_local_timer_setup(); + local_irq_enable(); /* -- cgit v1.2.3 From 0b39db28b953945232719e7ff6fb802aa8a2be5f Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Mon, 28 Dec 2009 11:13:51 +0000 Subject: Blackfin: SMP: add PM/CPU hotplug support Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/mach-common/smp.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'arch/blackfin/mach-common/smp.c') diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index b343ab3764a1..efc47ffd066d 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -344,8 +344,11 @@ void smp_send_stop(void) int __cpuinit __cpu_up(unsigned int cpu) { - struct task_struct *idle; int ret; + static struct task_struct *idle; + + if (idle) + free_task(idle); idle = fork_idle(cpu); if (IS_ERR(idle)) { @@ -354,7 +357,6 @@ int __cpuinit __cpu_up(unsigned int cpu) } secondary_stack = task_stack_page(idle) + THREAD_SIZE; - smp_wmb(); ret = platform_boot_secondary(cpu, idle); @@ -413,7 +415,6 @@ void __cpuinit secondary_start_kernel(void) atomic_inc(&mm->mm_users); atomic_inc(&mm->mm_count); current->active_mm = mm; - BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */ preempt_disable(); @@ -495,3 +496,34 @@ void resync_core_dcache(void) } EXPORT_SYMBOL(resync_core_dcache); #endif + +#ifdef CONFIG_HOTPLUG_CPU +int __cpuexit __cpu_disable(void) +{ + unsigned int cpu = smp_processor_id(); + + if (cpu == 0) + return -EPERM; + + set_cpu_online(cpu, false); + return 0; +} + +static DECLARE_COMPLETION(cpu_killed); + +int __cpuexit __cpu_die(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +void cpu_die(void) +{ + complete(&cpu_killed); + + atomic_dec(&init_mm.mm_users); + atomic_dec(&init_mm.mm_count); + + local_irq_disable(); + platform_cpu_die(); +} +#endif -- cgit v1.2.3 From 718340f62900ed44046d2b0f74d0dec7cf844194 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Mon, 1 Feb 2010 06:07:50 +0000 Subject: Blackfin: rewrite resync_core_{i,d}cache() SMP logic to avoid per_cpu data This functions are implicitly called by core functions like cpu_relax(), and since those functions may be called early on before common code has initialized the per-cpu data area, we need to tweak the stats gathering. Now the statistics are maintained in common bss which makes these funcs safe to use as soon as the C runtime env is setup. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/mach-common/smp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/mach-common/smp.c') diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index efc47ffd066d..7803f22d2ca7 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -474,24 +474,26 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end) EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); #ifdef __ARCH_SYNC_CORE_ICACHE +unsigned long icache_invld_count[NR_CPUS]; void resync_core_icache(void) { unsigned int cpu = get_cpu(); blackfin_invalidate_entire_icache(); - ++per_cpu(cpu_data, cpu).icache_invld_count; + icache_invld_count[cpu]++; put_cpu(); } EXPORT_SYMBOL(resync_core_icache); #endif #ifdef __ARCH_SYNC_CORE_DCACHE +unsigned long dcache_invld_count[NR_CPUS]; unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); void resync_core_dcache(void) { unsigned int cpu = get_cpu(); blackfin_invalidate_entire_dcache(); - ++per_cpu(cpu_data, cpu).dcache_invld_count; + dcache_invld_count[cpu]++; put_cpu(); } EXPORT_SYMBOL(resync_core_dcache); -- cgit v1.2.3