From f821e349cf2539bc7752652ef7b60030c1fc49fb Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Sep 2012 12:07:21 +1000 Subject: m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x Remove the last address definitions relative to the IPSBAR peripheral region for the ColdFire 527x family. This involved cleaning up some magic numbers used in the code part, and making them proper register definitions in the 527x specific header. This is part of the process of cleaning up the ColdFire register definitions to make them consistently use absolute addresses for the primary registers. This will reduce the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 52 ++++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 18 deletions(-) (limited to 'arch/m68k/include/asm/m527xsim.h') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 71aa5104d3d6..6335e4298dc8 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -194,9 +194,23 @@ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE +/* + * Port Pin Assignment registers. + */ +#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) +#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) +#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) +#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) +#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) +#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) +#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) -#endif + +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x0ff0 +#define UART2_ENABLE_MASK 0x3000 +#endif /* CONFIG_M5271 */ #ifdef CONFIG_M5275 #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) @@ -289,8 +303,26 @@ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE +/* + * Port Pin Assignment registers. + */ +#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070) +#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071) +#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072) +#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076) +#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078) +#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079) +#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A) +#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) -#endif +#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) +#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082) +#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084) + +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x00f0 +#define UART2_ENABLE_MASK 0x3f00 +#endif /* CONFIG_M5275 */ /* * PIT timer base addresses. @@ -310,22 +342,6 @@ #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) -/* - * GPIO pins setups to enable the UARTs. - */ -#ifdef CONFIG_M5271 -#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ -#define UART0_ENABLE_MASK 0x000f -#define UART1_ENABLE_MASK 0x0ff0 -#define UART2_ENABLE_MASK 0x3000 -#endif -#ifdef CONFIG_M5275 -#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ -#define UART0_ENABLE_MASK 0x000f -#define UART1_ENABLE_MASK 0x00f0 -#define UART2_ENABLE_MASK 0x3f00 -#endif - /* * Reset Control Unit (relative to IPSBAR). */ -- cgit v1.2.3 From 39dc5b7fcebe3cca65b775f743416107ec321e0b Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Sep 2012 15:38:15 +1000 Subject: m68knommu: fix inconsistent formating in ColdFire 527x definitions Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/m68k/include/asm/m527xsim.h') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 6335e4298dc8..1bebbe78055a 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -184,15 +184,15 @@ /* * Generic GPIO support */ -#define MCFGPIO_PODR MCFGPIO_PODR_ADDR -#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR -#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR -#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR +#define MCFGPIO_PODR MCFGPIO_PODR_ADDR +#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR +#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR +#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR -#define MCFGPIO_PIN_MAX 100 -#define MCFGPIO_IRQ_MAX 8 -#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE +#define MCFGPIO_PIN_MAX 100 +#define MCFGPIO_IRQ_MAX 8 +#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE /* * Port Pin Assignment registers. @@ -293,15 +293,15 @@ /* * Generic GPIO support */ -#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL -#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL - -#define MCFGPIO_PIN_MAX 148 -#define MCFGPIO_IRQ_MAX 8 -#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE +#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL +#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL +#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL +#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL + +#define MCFGPIO_PIN_MAX 148 +#define MCFGPIO_IRQ_MAX 8 +#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE /* * Port Pin Assignment registers. -- cgit v1.2.3