From f7a20ba06435d067247bd50a15a1d550b9b3fc7d Mon Sep 17 00:00:00 2001 From: "sfking@fdwdc.com" Date: Fri, 19 Jun 2009 18:11:09 -0700 Subject: generic GPIO support for the Freescale Coldfire 5307. Add support for the 5307. Signed-off-by: Steven King Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5307sim.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include/asm/m5307sim.h') diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 5886728409c0..6a1870c925a6 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -90,8 +90,15 @@ #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ -#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ +#define MCFSIM_PADDR (MCF_MBAR + 0x244) +#define MCFSIM_PADAT (MCF_MBAR + 0x248) + +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX 16 +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 /* Definition offset address for CS2-7 -- old mask 5307 */ -- cgit v1.2.3 From f2154bef817ac3d0ea67b52526fd8e88898b66f9 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 19 May 2009 14:38:08 +1000 Subject: m68knommu: merge old ColdFire interrupt controller masking macros Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5307sim.h | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'arch/m68k/include/asm/m5307sim.h') diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 6a1870c925a6..60946225699d 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -124,23 +124,6 @@ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ -#if defined(CONFIG_M5307) -#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ -#endif - -/* - * Macro to set IMR register. It is 32 bits on the 5307. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - - /* * Some symbol defines for the Parallel Port Pin Assignment Register */ -- cgit v1.2.3 From 04b75b10dceadf937e3707ecc3dfccf6a076fd29 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 19 May 2009 14:52:40 +1000 Subject: m68knommu: simplify ColdFire "timers" clock initialization The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5307sim.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/m68k/include/asm/m5307sim.h') diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 60946225699d..c6830e5b54ce 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -124,6 +124,7 @@ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + /* * Some symbol defines for the Parallel Port Pin Assignment Register */ @@ -139,6 +140,11 @@ #define IRQ3_LEVEL6 0x40 #define IRQ1_LEVEL2 0x20 +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ /* * Define the Cache register flags. -- cgit v1.2.3