From d85b40948654dee3be1d8e43b0fce511c1b42d78 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 26 Oct 2011 09:51:55 +0200 Subject: m68k: Fall back to __gpio_to_irq() for non-arch GPIOs gpiolib provides __gpio_to_irq() to map gpiolib gpios to interrupts - hook that up on m68k. Signed-off-by: Mark Brown Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index b2046839f4b2..00d0071de4c3 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -225,7 +225,8 @@ static inline void gpio_set_value(unsigned gpio, int value) static inline int gpio_to_irq(unsigned gpio) { - return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE : -EINVAL; + return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE + : __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned irq) -- cgit v1.2.3 From 8d362b0dea1a35bea8d7d281317eb7ccb713edcb Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 2 Sep 2011 14:20:06 +1000 Subject: m68k: remove duplicate asm offset for task thread.info We have a duplicate name and definition for the offset of the thread.info struct within the task struct in our asm-offsets.c code. Remove one of them, and consolidate to use a single define, TASK_INFO. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/thread_info.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h index 790988967ba7..e4e2159ca6ec 100644 --- a/arch/m68k/include/asm/thread_info.h +++ b/arch/m68k/include/asm/thread_info.h @@ -57,7 +57,7 @@ struct thread_info { #define task_thread_info(tsk) ((struct thread_info *) NULL) #else #include -#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_TINFO)) +#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_INFO)) #endif #define init_thread_info (init_task.thread.info) -- cgit v1.2.3 From d25ba98afce7c87afa39f553a3ff8effed87db03 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 2 Sep 2011 14:29:34 +1000 Subject: m68k: remove thread_info struct from thread struct Currently on m68k we have a comeplete thread_info structure stored inside of the thread_struct, and we also have it in the initial part of the kernel stack. Mostly the code currently uses the one inside of the thread_struct, only using the "task" pointer from the stack based one. This is wasteful and confusing, we should only have the single instance of thread_info inside the stack page. And this is the norm for all other architectures. This change makes m68k handle thread_info consistently on both MMU enabled and non-MMU setups. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/processor.h | 2 -- arch/m68k/include/asm/thread_info.h | 30 ------------------------------ 2 files changed, 32 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 568facf30276..7ec06096a6fb 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -88,14 +88,12 @@ struct thread_struct { unsigned long fp[8*3]; unsigned long fpcntl[3]; /* fp control regs */ unsigned char fpstate[FPSTATESIZE]; /* floating point state */ - struct thread_info info; }; #define INIT_THREAD { \ .ksp = sizeof(init_stack) + (unsigned long) init_stack, \ .sr = PS_S, \ .fs = __KERNEL_DS, \ - .info = INIT_THREAD_INFO(init_task), \ } #ifdef CONFIG_MMU diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h index e4e2159ca6ec..01cef3ceff46 100644 --- a/arch/m68k/include/asm/thread_info.h +++ b/arch/m68k/include/asm/thread_info.h @@ -47,34 +47,6 @@ struct thread_info { #define init_stack (init_thread_union.stack) -#ifdef CONFIG_MMU - -#ifndef __ASSEMBLY__ -#include -#endif - -#ifdef ASM_OFFSETS_C -#define task_thread_info(tsk) ((struct thread_info *) NULL) -#else -#include -#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_INFO)) -#endif - -#define init_thread_info (init_task.thread.info) -#define task_stack_page(tsk) ((tsk)->stack) -#define current_thread_info() task_thread_info(current) - -#define __HAVE_THREAD_FUNCTIONS - -#define setup_thread_stack(p, org) ({ \ - *(struct task_struct **)(p)->stack = (p); \ - task_thread_info(p)->task = (p); \ -}) - -#define end_of_stack(p) ((unsigned long *)(p)->stack + 1) - -#else /* !CONFIG_MMU */ - #ifndef __ASSEMBLY__ /* how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) @@ -92,8 +64,6 @@ static inline struct thread_info *current_thread_info(void) #define init_thread_info (init_thread_union.thread_info) -#endif /* CONFIG_MMU */ - /* entry.S relies on these definitions! * bits 0-7 are tested at every exception exit * bits 8-15 are also tested at syscall exit -- cgit v1.2.3 From e87c09a899d38d1b6858e010c22a1200fb77965d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 13 Oct 2011 16:59:55 +1000 Subject: m68k: print memory layout info in boot log Output a table of the kernel memory regions at boot time. This is taken directly from the ARM architecture code that does this. The table looks like this: Virtual kernel memory layout: vector : 0x00000000 - 0x00000400 ( 0 KiB) kmap : 0xd0000000 - 0xe0000000 ( 256 MiB) vmalloc : 0xc0000000 - 0xcfffffff ( 255 MiB) lowmem : 0x00000000 - 0x02000000 ( 32 MiB) .init : 0x00128000 - 0x00134000 ( 48 KiB) .text : 0x00020000 - 0x00118d54 ( 996 KiB) .data : 0x00118d60 - 0x00126000 ( 53 KiB) .bss : 0x00134000 - 0x001413e0 ( 53 KiB) This has been very useful while debugging the ColdFire virtual memory support code. But in general I think it is nice to know extacly where the kernel has layed everything out on boot. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/traps.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/traps.h b/arch/m68k/include/asm/traps.h index 151068f64f44..4aff3358fbaf 100644 --- a/arch/m68k/include/asm/traps.h +++ b/arch/m68k/include/asm/traps.h @@ -18,6 +18,7 @@ typedef void (*e_vector)(void); extern e_vector vectors[]; +extern e_vector *_ramvec; asmlinkage void auto_inthandler(void); asmlinkage void user_inthandler(void); -- cgit v1.2.3 From 479badc364b52774d77264aaf81f4d4b375a4a97 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 2 Nov 2011 15:44:42 +1000 Subject: m68k: make fp register stores consistent for m68k and ColdFire There is no reason we can't make the saved fp registers the same for all m68k types and ColdFire. There is a little wasted space, but the code consistency and cleanliness is a big win. sigcontext.h is an exported header, but currently there is no in-mainline users of the !__uClinux__ and __mcoldfire__ case that this change effects. Even better this change actually makes this structure consistent with the out-of-mainline ColdFire/MMU code. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/sigcontext.h | 4 ---- arch/m68k/include/asm/ucontext.h | 4 ---- 2 files changed, 8 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/sigcontext.h b/arch/m68k/include/asm/sigcontext.h index a29dd74a17cb..523db2a51cf3 100644 --- a/arch/m68k/include/asm/sigcontext.h +++ b/arch/m68k/include/asm/sigcontext.h @@ -15,11 +15,7 @@ struct sigcontext { unsigned long sc_pc; unsigned short sc_formatvec; #ifndef __uClinux__ -# ifdef __mcoldfire__ - unsigned long sc_fpregs[2][2]; /* room for two fp registers */ -# else unsigned long sc_fpregs[2*3]; /* room for two fp registers */ -# endif unsigned long sc_fpcntl[3]; unsigned char sc_fpstate[216]; #endif diff --git a/arch/m68k/include/asm/ucontext.h b/arch/m68k/include/asm/ucontext.h index 00dcc5176c57..e4e22669edc0 100644 --- a/arch/m68k/include/asm/ucontext.h +++ b/arch/m68k/include/asm/ucontext.h @@ -7,11 +7,7 @@ typedef greg_t gregset_t[NGREG]; typedef struct fpregset { int f_fpcntl[3]; -#ifdef __mcoldfire__ - int f_fpregs[8][2]; -#else int f_fpregs[8*3]; -#endif } fpregset_t; struct mcontext { -- cgit v1.2.3 From 7f73bafc4630a450ebe8b021efa14781ffd992b1 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Oct 2011 15:49:19 +1000 Subject: m68k: simpler m68k and ColdFire CPU's can use generic csum code We have two implementations of the IP checksuming code for the m68k arch. One uses the more advanced instructions available in 68020 and above processors, the other uses the simpler instructions available on the original 68000 processors and the modern ColdFire processors. This simpler code is pretty much the same as the generic lib implementation of the IP csum functions. So lets just switch over to using that. That means we can completely remove the checksum_no.c file, and only have the local fast code used for the more complex 68k CPU family members. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/checksum.h | 31 +++++-------------------------- 1 file changed, 5 insertions(+), 26 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h index ec514485c8b6..2f88d867c711 100644 --- a/arch/m68k/include/asm/checksum.h +++ b/arch/m68k/include/asm/checksum.h @@ -3,6 +3,10 @@ #include +#ifdef CONFIG_GENERIC_CSUM +#include +#else + /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) @@ -34,30 +38,6 @@ extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum); - -#ifdef CONFIG_COLDFIRE - -/* - * The ColdFire cores don't support all the 68k instructions used - * in the optimized checksum code below. So it reverts back to using - * more standard C coded checksums. The fast checksum code is - * significantly larger than the optimized version, so it is not - * inlined here. - */ -__sum16 ip_fast_csum(const void *iph, unsigned int ihl); - -static inline __sum16 csum_fold(__wsum sum) -{ - unsigned int tmp = (__force u32)sum; - - tmp = (tmp & 0xffff) + (tmp >> 16); - tmp = (tmp & 0xffff) + (tmp >> 16); - - return (__force __sum16)~tmp; -} - -#else - /* * This is a version of ip_fast_csum() optimized for IP headers, * which always checksum on 4 octet boundaries. @@ -97,8 +77,6 @@ static inline __sum16 csum_fold(__wsum sum) return (__force __sum16)~sum; } -#endif /* CONFIG_COLDFIRE */ - static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, unsigned short proto, __wsum sum) @@ -167,4 +145,5 @@ csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, return csum_fold(sum); } +#endif /* CONFIG_GENERIC_CSUM */ #endif /* _M68K_CHECKSUM_H */ -- cgit v1.2.3 From 84f3fb7a2aadeda3c0a34e61591a8eccf5e367b4 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 11 Nov 2011 15:13:08 +1000 Subject: m68k: handle presence of 64bit mul/div instructions cleanly The traditional 68000 processors and the newer reduced instruction set ColdFire processors do not support the 32*32->64 multiply or the 64/32->32 divide instructions. This is not a difference based on the presence of a hardware MMU or not. Create a new config symbol to mark that a CPU type doesn't support the longer multiply/divide instructions. Use this then as a basis for using the fast 64bit based divide (in div64.h) and for linking in the extra libgcc functions that may be required (mulsi3, divsi3, etc). Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/div64.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h index edb66148a71d..444ea8a09e9f 100644 --- a/arch/m68k/include/asm/div64.h +++ b/arch/m68k/include/asm/div64.h @@ -1,7 +1,9 @@ #ifndef _M68K_DIV64_H #define _M68K_DIV64_H -#ifdef CONFIG_MMU +#ifdef CONFIG_CPU_HAS_NO_MULDIV64 +#include +#else #include @@ -27,8 +29,6 @@ __rem; \ }) -#else -#include -#endif /* CONFIG_MMU */ +#endif /* CONFIG_CPU_HAS_NO_MULDIV64 */ #endif /* _M68K_DIV64_H */ -- cgit v1.2.3 From 45f9e2cdcd958691cc691ad1ca2b1e8b9f535967 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 25 Nov 2011 16:42:31 +1000 Subject: m68knommu: remove unused anchor.h include file The code that used the anchor.h include file has long been removed from the kernel. Remove it too. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/anchor.h | 112 ----------------------------------------- 1 file changed, 112 deletions(-) delete mode 100644 arch/m68k/include/asm/anchor.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/anchor.h b/arch/m68k/include/asm/anchor.h deleted file mode 100644 index 871c0d5cfc3d..000000000000 --- a/arch/m68k/include/asm/anchor.h +++ /dev/null @@ -1,112 +0,0 @@ -/****************************************************************************/ - -/* - * anchor.h -- Anchor CO-MEM Lite PCI host bridge part. - * - * (C) Copyright 2000, Moreton Bay (www.moreton.com.au) - */ - -/****************************************************************************/ -#ifndef anchor_h -#define anchor_h -/****************************************************************************/ - -/* - * Define basic addressing info. - */ -#if defined(CONFIG_M5407C3) -#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */ -#define COMEM_IRQ 25 /* IRQ of anchor part */ -#else -#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */ -#define COMEM_IRQ 25 /* IRQ of anchor part */ -#endif - -/****************************************************************************/ - -/* - * 4-byte registers of CO-MEM, so adjust register addresses for - * easy access. Handy macro for word access too. - */ -#define LREG(a) ((a) >> 2) -#define WREG(a) ((a) >> 1) - - -/* - * Define base addresses within CO-MEM Lite register address space. - */ -#define COMEM_I2O 0x0000 /* I2O registers */ -#define COMEM_OPREGS 0x0400 /* Operation registers */ -#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */ -#define COMEM_SHMEM 0x4000 /* Shared memory region */ - -#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */ - - -/* - * Define CO-MEM Registers. - */ -#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */ -#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */ -#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */ -#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */ -#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */ -#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */ -#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */ -#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */ - -#define COMEM_DAHBASE 0x0460 /* Direct access base address */ - -#define COMEM_NVCMD 0x04a0 /* I2C serial command */ -#define COMEM_NVREAD 0x04a4 /* I2C serial read */ -#define COMEM_NVSTAT 0x04a8 /* I2C status */ - -#define COMEM_DMALBASE 0x04b0 /* DMA local base address */ -#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */ -#define COMEM_DMASIZE 0x04b8 /* DMA size */ -#define COMEM_DMACTL 0x04bc /* DMA control */ - -#define COMEM_HCTL 0x04e0 /* Host control */ -#define COMEM_HINT 0x04e4 /* Host interrupt control/status */ -#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */ -#define COMEM_LINT 0x04f4 /* Local interrupt contole status */ -#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */ - -#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */ - - -/* - * Commands and flags for use with Direct Access Register. - */ -#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */ -#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */ -#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */ -#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */ -#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */ -#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */ -#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */ -#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */ - -#define COMEM_DA_ADDR(a) ((a) & 0xffffe000) - -#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff) - - -/* - * The PCI bus will be limited in what slots will actually be used. - * Define valid device numbers for different boards. - */ -#if defined(CONFIG_M5407C3) -#define COMEM_MINDEV 14 /* Minimum valid DEVICE */ -#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */ -#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */ -#else -#define COMEM_MINDEV 0 /* Minimum valid DEVICE */ -#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */ -#endif - -#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */ - - -/****************************************************************************/ -#endif /* anchor_h */ -- cgit v1.2.3 From 59dbb3b168465e48e3a72b635ee0c184fa5c55aa Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 11:32:41 +1000 Subject: m68k: add machine and CPU definitions for ColdFire cores Create machine and CPU definitions to support the ColdFire CPU family members that have a virtual memory management unit. The ColdFire V4e core contains an MMU, and it is quite different to any other 68k family members. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/setup.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h index 4dfb3952b375..00c2c5397d37 100644 --- a/arch/m68k/include/asm/setup.h +++ b/arch/m68k/include/asm/setup.h @@ -40,6 +40,7 @@ #define MACH_HP300 9 #define MACH_Q40 10 #define MACH_SUN3X 11 +#define MACH_M54XX 12 #define COMMAND_LINE_SIZE 256 @@ -211,23 +212,27 @@ extern unsigned long m68k_machtype; #define CPUB_68030 1 #define CPUB_68040 2 #define CPUB_68060 3 +#define CPUB_COLDFIRE 4 #define CPU_68020 (1< Date: Fri, 14 Oct 2011 12:01:22 +1000 Subject: m68k: definitions for the ColdFire V4e MMU hardware Basic register level definitions to support the internal MMU of the V4e ColdFire cores. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/mcfmmu.h | 110 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 arch/m68k/include/asm/mcfmmu.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/mcfmmu.h b/arch/m68k/include/asm/mcfmmu.h new file mode 100644 index 000000000000..8fdcfedd5d15 --- /dev/null +++ b/arch/m68k/include/asm/mcfmmu.h @@ -0,0 +1,110 @@ +/* + * mcfmmu.h -- definitions for the ColdFire v4e MMU + * + * (C) Copyright 2011, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef MCFMMU_H +#define MCFMMU_H + +/* + * The MMU support registers are mapped into the address space using + * the processor MMUBASE register. We used a fixed address for mapping, + * there doesn't seem any need to make this configurable yet. + */ +#define MMUBASE 0xfe000000 + +/* + * The support registers of the MMU. Names are the sames as those + * used in the Freescale v4e documentation. + */ +#define MMUCR (MMUBASE + 0x00) /* Control register */ +#define MMUOR (MMUBASE + 0x04) /* Operation register */ +#define MMUSR (MMUBASE + 0x08) /* Status register */ +#define MMUAR (MMUBASE + 0x10) /* TLB Address register */ +#define MMUTR (MMUBASE + 0x14) /* TLB Tag register */ +#define MMUDR (MMUBASE + 0x18) /* TLB Data register */ + +/* + * MMU Control register bit flags + */ +#define MMUCR_EN 0x00000001 /* Virtual mode enable */ +#define MMUCR_ASM 0x00000002 /* Address space mode */ + +/* + * MMU Operation register. + */ +#define MMUOR_UAA 0x00000001 /* Update allocatiom address */ +#define MMUOR_ACC 0x00000002 /* TLB access */ +#define MMUOR_RD 0x00000004 /* TLB access read */ +#define MMUOR_WR 0x00000000 /* TLB access write */ +#define MMUOR_ADR 0x00000008 /* TLB address select */ +#define MMUOR_ITLB 0x00000010 /* ITLB operation */ +#define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */ +#define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */ +#define MMUOR_CA 0x00000080 /* Clear all TLBs */ +#define MMUOR_STLB 0x00000100 /* Search TLBs */ +#define MMUOR_AAN 16 /* TLB allocation address */ +#define MMUOR_AAMASK 0xffff0000 /* AA mask */ + +/* + * MMU Status register. + */ +#define MMUSR_HIT 0x00000002 /* Search TLB hit */ +#define MMUSR_WF 0x00000008 /* Write access fault */ +#define MMUSR_RF 0x00000010 /* Read access fault */ +#define MMUSR_SPF 0x00000020 /* Supervisor protect fault */ + +/* + * MMU Read/Write Tag register. + */ +#define MMUTR_V 0x00000001 /* Valid */ +#define MMUTR_SG 0x00000002 /* Shared global */ +#define MMUTR_IDN 2 /* Address Space ID */ +#define MMUTR_IDMASK 0x000003fc /* ASID mask */ +#define MMUTR_VAN 10 /* Virtual Address */ +#define MMUTR_VAMASK 0xfffffc00 /* VA mask */ + +/* + * MMU Read/Write Data register. + */ +#define MMUDR_LK 0x00000002 /* Lock entry */ +#define MMUDR_X 0x00000004 /* Execute access enable */ +#define MMUDR_W 0x00000008 /* Write access enable */ +#define MMUDR_R 0x00000010 /* Read access enable */ +#define MMUDR_SP 0x00000020 /* Supervisor access enable */ +#define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */ +#define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */ +#define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */ +#define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */ +#define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */ +#define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */ +#define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */ +#define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */ +#define MMUDR_PAN 10 /* Physical address */ +#define MMUDR_PAMASK 0xfffffc00 /* PA mask */ + +#ifndef __ASSEMBLY__ + +/* + * Simple access functions for the MMU registers. Nothing fancy + * currently required, just simple 32bit access. + */ +static inline u32 mmu_read(u32 a) +{ + return *((volatile u32 *) a); +} + +static inline void mmu_write(u32 a, u32 v) +{ + *((volatile u32 *) a) = v; + __asm__ __volatile__ ("nop"); +} + +#endif + +#endif /* MCFMMU_H */ -- cgit v1.2.3 From 78ccdffc937319f4f7ffc13684c114100c727c21 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 14:22:22 +1000 Subject: m68k: make interrupt definitions conditional on correct CPU types The interrupt handling support defines and code is not so much conditional on an MMU being present (CONFIG_MMU), as it is on which type of CPU we are building for. So make the code conditional on the CPU types instead. The current irq.h is mostly specific to the interrupt code for the 680x0 CPUs, so it should only be used for them. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/irq.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h index 6198df5ff245..0e89fa05de0e 100644 --- a/arch/m68k/include/asm/irq.h +++ b/arch/m68k/include/asm/irq.h @@ -25,7 +25,8 @@ #define NR_IRQS 0 #endif -#ifdef CONFIG_MMU +#if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \ + defined(CONFIG_M68040) || defined(CONFIG_M68060) /* * Interrupt source definitions @@ -80,7 +81,7 @@ extern unsigned int irq_canonicalize(unsigned int irq); #else #define irq_canonicalize(irq) (irq) -#endif /* CONFIG_MMU */ +#endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */ asmlinkage void do_IRQ(int irq, struct pt_regs *regs); extern atomic_t irq_err_count; -- cgit v1.2.3 From 2c9b82adb5ea65745d5d73d97bb0e1cc16cba4a0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 14:36:41 +1000 Subject: m68k: add TASK definitions for ColdFires running with MMU Add appropriate TASK_SIZE and TASK_UNMAPPED_BASE definitions for running on ColdFire V4e cores with MMU enabled. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/processor.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 7ec06096a6fb..46460fa15d5c 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -48,10 +48,12 @@ static inline void wrusp(unsigned long usp) * so don't change it unless you know what you are doing. */ #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 -#define TASK_SIZE (0xF0000000UL) -#else +#if defined(CONFIG_COLDFIRE) +#define TASK_SIZE (0xC0000000UL) +#elif defined(CONFIG_SUN3) #define TASK_SIZE (0x0E000000UL) +#else +#define TASK_SIZE (0xF0000000UL) #endif #else #define TASK_SIZE (0xFFFFFFFFUL) @@ -66,10 +68,12 @@ static inline void wrusp(unsigned long usp) * space during mmap's. */ #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 -#define TASK_UNMAPPED_BASE 0xC0000000UL -#else +#if defined(CONFIG_COLDFIRE) +#define TASK_UNMAPPED_BASE 0x60000000UL +#elif defined(CONFIG_SUN3) #define TASK_UNMAPPED_BASE 0x0A000000UL +#else +#define TASK_UNMAPPED_BASE 0xC0000000UL #endif #define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr) #else -- cgit v1.2.3 From e08d703cc2ab6e47dbd10a74eb029f7dfa93d71d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 14:43:30 +1000 Subject: m68k: modify user space access functions to support ColdFire CPUs Modify the user space access functions to support the ColdFire V4e cores running with MMU enabled. The ColdFire processors do not support the "moves" instruction used by the traditional 680x0 processors for moving data into and out of another address space. They only support the notion of a single address space, and you use the usual "move" instruction to access that. Create a new config symbol (CONFIG_CPU_HAS_ADDRESS_SPACES) to mark the CPU types that support separate address spaces, and thus also support the sfc/dfc registers and the "moves" instruction that go along with that. The code is almost identical for user space access, so lets just use a define to choose either the "move" or "moves" in the assembler code. Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/segment.h | 4 ++-- arch/m68k/include/asm/uaccess_mm.h | 42 ++++++++++++++++++++++++++------------ 2 files changed, 31 insertions(+), 15 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h index ee959219fdfe..1a142e9ceaad 100644 --- a/arch/m68k/include/asm/segment.h +++ b/arch/m68k/include/asm/segment.h @@ -31,7 +31,7 @@ typedef struct { static inline mm_segment_t get_fs(void) { -#ifdef CONFIG_MMU +#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES mm_segment_t _v; __asm__ ("movec %/dfc,%0":"=r" (_v.seg):); @@ -49,7 +49,7 @@ static inline mm_segment_t get_ds(void) static inline void set_fs(mm_segment_t val) { -#ifdef CONFIG_MMU +#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES __asm__ __volatile__ ("movec %0,%/sfc\n\t" "movec %0,%/dfc\n\t" : /* no outputs */ : "r" (val.seg) : "memory"); diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h index 7107f3fbdbb6..9c80cd515b20 100644 --- a/arch/m68k/include/asm/uaccess_mm.h +++ b/arch/m68k/include/asm/uaccess_mm.h @@ -20,6 +20,22 @@ static inline int access_ok(int type, const void __user *addr, return 1; } +/* + * Not all varients of the 68k family support the notion of address spaces. + * The traditional 680x0 parts do, and they use the sfc/dfc registers and + * the "moves" instruction to access user space from kernel space. Other + * family members like ColdFire don't support this, and only have a single + * address space, and use the usual "move" instruction for user space access. + * + * Outside of this difference the user space access functions are the same. + * So lets keep the code simple and just define in what we need to use. + */ +#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES +#define MOVES "moves" +#else +#define MOVES "move" +#endif + /* * The exception table consists of pairs of addresses: the first is the * address of an instruction that is allowed to fault, and the second is @@ -43,7 +59,7 @@ extern int __get_user_bad(void); #define __put_user_asm(res, x, ptr, bwl, reg, err) \ asm volatile ("\n" \ - "1: moves."#bwl" %2,%1\n" \ + "1: "MOVES"."#bwl" %2,%1\n" \ "2:\n" \ " .section .fixup,\"ax\"\n" \ " .even\n" \ @@ -83,8 +99,8 @@ asm volatile ("\n" \ { \ const void __user *__pu_ptr = (ptr); \ asm volatile ("\n" \ - "1: moves.l %2,(%1)+\n" \ - "2: moves.l %R2,(%1)\n" \ + "1: "MOVES".l %2,(%1)+\n" \ + "2: "MOVES".l %R2,(%1)\n" \ "3:\n" \ " .section .fixup,\"ax\"\n" \ " .even\n" \ @@ -115,12 +131,12 @@ asm volatile ("\n" \ #define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ type __gu_val; \ asm volatile ("\n" \ - "1: moves."#bwl" %2,%1\n" \ + "1: "MOVES"."#bwl" %2,%1\n" \ "2:\n" \ " .section .fixup,\"ax\"\n" \ " .even\n" \ "10: move.l %3,%0\n" \ - " sub."#bwl" %1,%1\n" \ + " sub.l %1,%1\n" \ " jra 2b\n" \ " .previous\n" \ "\n" \ @@ -152,8 +168,8 @@ asm volatile ("\n" \ const void *__gu_ptr = (ptr); \ u64 __gu_val; \ asm volatile ("\n" \ - "1: moves.l (%2)+,%1\n" \ - "2: moves.l (%2),%R1\n" \ + "1: "MOVES".l (%2)+,%1\n" \ + "2: "MOVES".l (%2),%R1\n" \ "3:\n" \ " .section .fixup,\"ax\"\n" \ " .even\n" \ @@ -188,12 +204,12 @@ unsigned long __generic_copy_to_user(void __user *to, const void *from, unsigned #define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ asm volatile ("\n" \ - "1: moves."#s1" (%2)+,%3\n" \ + "1: "MOVES"."#s1" (%2)+,%3\n" \ " move."#s1" %3,(%1)+\n" \ - "2: moves."#s2" (%2)+,%3\n" \ + "2: "MOVES"."#s2" (%2)+,%3\n" \ " move."#s2" %3,(%1)+\n" \ " .ifnc \""#s3"\",\"\"\n" \ - "3: moves."#s3" (%2)+,%3\n" \ + "3: "MOVES"."#s3" (%2)+,%3\n" \ " move."#s3" %3,(%1)+\n" \ " .endif\n" \ "4:\n" \ @@ -269,13 +285,13 @@ __constant_copy_from_user(void *to, const void __user *from, unsigned long n) #define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ asm volatile ("\n" \ " move."#s1" (%2)+,%3\n" \ - "11: moves."#s1" %3,(%1)+\n" \ + "11: "MOVES"."#s1" %3,(%1)+\n" \ "12: move."#s2" (%2)+,%3\n" \ - "21: moves."#s2" %3,(%1)+\n" \ + "21: "MOVES"."#s2" %3,(%1)+\n" \ "22:\n" \ " .ifnc \""#s3"\",\"\"\n" \ " move."#s3" (%2)+,%3\n" \ - "31: moves."#s3" %3,(%1)+\n" \ + "31: "MOVES"."#s3" %3,(%1)+\n" \ "32:\n" \ " .endif\n" \ "4:\n" \ -- cgit v1.2.3 From feb1ee759522eb67e7733fe5b59bd17420f4d2d8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 17:31:26 +1000 Subject: m68k: use addr_limit checking for m68k CPUs that do no support address spaces The ColdFire CPU family, and the original 68000, do not support separate address spaces like the other 680x0 CPU types. Modify the set_fs()/get_fs() functions and macros to use a thread_info addr_limit for address space checking. This is pretty much what all other architectures that do not support separate setable address spaces do. Signed-off-by: Alexander Stein Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/segment.h | 30 ++++++++++++++++-------------- arch/m68k/include/asm/thread_info.h | 3 +++ 2 files changed, 19 insertions(+), 14 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h index 1a142e9ceaad..0fa80e97ed2d 100644 --- a/arch/m68k/include/asm/segment.h +++ b/arch/m68k/include/asm/segment.h @@ -22,23 +22,26 @@ typedef struct { } mm_segment_t; #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -#define USER_DS MAKE_MM_SEG(__USER_DS) -#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) +#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES /* * Get/set the SFC/DFC registers for MOVES instructions */ +#define USER_DS MAKE_MM_SEG(__USER_DS) +#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) static inline mm_segment_t get_fs(void) { -#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES mm_segment_t _v; __asm__ ("movec %/dfc,%0":"=r" (_v.seg):); - return _v; -#else - return USER_DS; -#endif +} + +static inline void set_fs(mm_segment_t val) +{ + __asm__ __volatile__ ("movec %0,%/sfc\n\t" + "movec %0,%/dfc\n\t" + : /* no outputs */ : "r" (val.seg) : "memory"); } static inline mm_segment_t get_ds(void) @@ -47,14 +50,13 @@ static inline mm_segment_t get_ds(void) return KERNEL_DS; } -static inline void set_fs(mm_segment_t val) -{ -#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES - __asm__ __volatile__ ("movec %0,%/sfc\n\t" - "movec %0,%/dfc\n\t" - : /* no outputs */ : "r" (val.seg) : "memory"); +#else +#define USER_DS MAKE_MM_SEG(TASK_SIZE) +#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) #endif -} #define segment_eq(a,b) ((a).seg == (b).seg) diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h index 01cef3ceff46..29fa6da4f17c 100644 --- a/arch/m68k/include/asm/thread_info.h +++ b/arch/m68k/include/asm/thread_info.h @@ -3,6 +3,7 @@ #include #include +#include /* * On machines with 4k pages we default to an 8k thread size, though we @@ -26,6 +27,7 @@ struct thread_info { struct task_struct *task; /* main task structure */ unsigned long flags; struct exec_domain *exec_domain; /* execution domain */ + mm_segment_t addr_limit; /* thread address space */ int preempt_count; /* 0 => preemptable, <0 => BUG */ __u32 cpu; /* should always be 0 on m68k */ unsigned long tp_value; /* thread pointer */ @@ -39,6 +41,7 @@ struct thread_info { { \ .task = &tsk, \ .exec_domain = &default_exec_domain, \ + .addr_limit = KERNEL_DS, \ .preempt_count = INIT_PREEMPT_COUNT, \ .restart_block = { \ .fn = do_no_restart_syscall, \ -- cgit v1.2.3 From 88be3515934004d271398129ba7145635e95127e Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 15:06:22 +1000 Subject: m68k: add ColdFire 54xx CPU MMU memory init code Add code to the 54xx ColdFire CPU init to setup memory ready for the m68k paged memory start up. Some of the RAM variables that were specific to the non-mmu code paths now need to be used during this setup, so when CONFIG_MMU is enabled. Move these out of page_no.h and into page.h. Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/page.h | 4 ++++ arch/m68k/include/asm/page_no.h | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h index dfebb7c1e379..ba6c91d5f3a9 100644 --- a/arch/m68k/include/asm/page.h +++ b/arch/m68k/include/asm/page.h @@ -36,6 +36,10 @@ typedef struct page *pgtable_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) +extern unsigned long _rambase; +extern unsigned long _ramstart; +extern unsigned long _ramend; + #endif /* !__ASSEMBLY__ */ #ifdef CONFIG_MMU diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h index a8d1c60eb9ce..90595721185f 100644 --- a/arch/m68k/include/asm/page_no.h +++ b/arch/m68k/include/asm/page_no.h @@ -5,9 +5,6 @@ extern unsigned long memory_start; extern unsigned long memory_end; -extern unsigned long _rambase; -extern unsigned long _ramstart; -extern unsigned long _ramend; #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) #define free_user_page(page, addr) free_page(addr) -- cgit v1.2.3 From bbc6f1ba509cf9cda42ce63bbd40afe577ab028e Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 15:41:56 +1000 Subject: m68k: set register a2 to current if MMU enabled on ColdFire Virtual memory m68k systems build with register a2 dedicated to being the current proc pointer (non-MMU don't do this). Add code to the ColdFire interrupt and exception processing to set this on entry, and at context switch time. We use the same GET_CURRENT() macro that MMU enabled code uses - modifying it so that the assembler is ColdFire clean. Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/entry.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h index c3c5a8643e15..622138dc7288 100644 --- a/arch/m68k/include/asm/entry.h +++ b/arch/m68k/include/asm/entry.h @@ -222,16 +222,24 @@ * Non-MMU systems do not reserve %a2 in this way, and this definition is * not used for them. */ +#ifdef CONFIG_MMU + #define curptr a2 #define GET_CURRENT(tmp) get_current tmp .macro get_current reg=%d0 movel %sp,\reg - andw #-THREAD_SIZE,\reg + andl #-THREAD_SIZE,\reg movel \reg,%curptr movel %curptr@,%curptr .endm +#else + +#define GET_CURRENT(tmp) + +#endif /* CONFIG_MMU */ + #else /* C source */ #define STR(X) STR1(X) -- cgit v1.2.3 From 91521c2ea6e3d5a790df40988101ad099ddbf7c8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 16:11:38 +1000 Subject: m68k: page table support definitions and code for ColdFire MMU The ColdFire V4e MMU is nothing like any of the other m68k MMU's. So we need to create a set of definitions and support routines for the kernels paging functions. This is largely taken from Freescales BSP code for this (though it was a 2.6.25 kernel). I have cleaned it up alot from the original. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/mcf_pgtable.h | 425 ++++++++++++++++++++++++++++++++++++ 1 file changed, 425 insertions(+) create mode 100644 arch/m68k/include/asm/mcf_pgtable.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h new file mode 100644 index 000000000000..756bde4fb4f8 --- /dev/null +++ b/arch/m68k/include/asm/mcf_pgtable.h @@ -0,0 +1,425 @@ +#ifndef _MCF_PGTABLE_H +#define _MCF_PGTABLE_H + +#include +#include + +/* + * MMUDR bits, in proper place. We write these directly into the MMUDR + * after masking from the pte. + */ +#define CF_PAGE_LOCKED MMUDR_LK /* 0x00000002 */ +#define CF_PAGE_EXEC MMUDR_X /* 0x00000004 */ +#define CF_PAGE_WRITABLE MMUDR_W /* 0x00000008 */ +#define CF_PAGE_READABLE MMUDR_R /* 0x00000010 */ +#define CF_PAGE_SYSTEM MMUDR_SP /* 0x00000020 */ +#define CF_PAGE_COPYBACK MMUDR_CM_CCB /* 0x00000040 */ +#define CF_PAGE_NOCACHE MMUDR_CM_NCP /* 0x00000080 */ + +#define CF_CACHEMASK (~MMUDR_CM_CCB) +#define CF_PAGE_MMUDR_MASK 0x000000fe + +#define _PAGE_NOCACHE030 CF_PAGE_NOCACHE + +/* + * MMUTR bits, need shifting down. + */ +#define CF_PAGE_MMUTR_MASK 0x00000c00 +#define CF_PAGE_MMUTR_SHIFT 10 + +#define CF_PAGE_VALID (MMUTR_V << CF_PAGE_MMUTR_SHIFT) +#define CF_PAGE_SHARED (MMUTR_SG << CF_PAGE_MMUTR_SHIFT) + +/* + * Fake bits, not implemented in CF, will get masked out before + * hitting hardware. + */ +#define CF_PAGE_DIRTY 0x00000001 +#define CF_PAGE_FILE 0x00000200 +#define CF_PAGE_ACCESSED 0x00001000 + +#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */ +#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */ +#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */ +#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */ +#define _DESCTYPE_MASK 0x003 +#define _CACHEMASK040 (~0x060) +#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ + +/* + * Externally used page protection values. + */ +#define _PAGE_PRESENT (CF_PAGE_VALID) +#define _PAGE_ACCESSED (CF_PAGE_ACCESSED) +#define _PAGE_DIRTY (CF_PAGE_DIRTY) +#define _PAGE_READWRITE (CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_SYSTEM \ + | CF_PAGE_SHARED) + +/* + * Compound page protection values. + */ +#define PAGE_NONE __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED) + +#define PAGE_SHARED __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED) + +#define PAGE_INIT __pgprot(CF_PAGE_VALID \ + | CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_EXEC \ + | CF_PAGE_SYSTEM) + +#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_EXEC \ + | CF_PAGE_SYSTEM) + +#define PAGE_COPY __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_DIRTY) + +/* + * Page protections for initialising protection_map. See mm/mmap.c + * for use. In general, the bit positions are xwr, and P-items are + * private, the S-items are shared. + */ +#define __P000 PAGE_NONE +#define __P001 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE) +#define __P010 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_WRITABLE) +#define __P011 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE) +#define __P100 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_EXEC) +#define __P101 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) +#define __P110 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_EXEC) +#define __P111 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_EXEC) + +#define __S000 PAGE_NONE +#define __S001 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE) +#define __S010 PAGE_SHARED +#define __S011 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE) +#define __S100 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_EXEC) +#define __S101 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) +#define __S110 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_EXEC) +#define __S111 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) + +#define PTE_MASK PAGE_MASK +#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY) + +#ifndef __ASSEMBLY__ + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); + return pte; +} + +#define pmd_set(pmdp, ptep) do {} while (0) + +static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) +{ + pgd_val(*pgdp) = virt_to_phys(pmdp); +} + +#define __pte_page(pte) ((unsigned long) (pte_val(pte) & PAGE_MASK)) +#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd))) + +static inline int pte_none(pte_t pte) +{ + return !pte_val(pte); +} + +static inline int pte_present(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_VALID; +} + +static inline void pte_clear(struct mm_struct *mm, unsigned long addr, + pte_t *ptep) +{ + pte_val(*ptep) = 0; +} + +#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) +#define pte_page(pte) virt_to_page(__pte_page(pte)) + +static inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); } +#define pmd_none(pmd) pmd_none2(&(pmd)) +static inline int pmd_bad2(pmd_t *pmd) { return 0; } +#define pmd_bad(pmd) pmd_bad2(&(pmd)) +#define pmd_present(pmd) (!pmd_none2(&(pmd))) +static inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; } + +static inline int pgd_none(pgd_t pgd) { return 0; } +static inline int pgd_bad(pgd_t pgd) { return 0; } +static inline int pgd_present(pgd_t pgd) { return 1; } +static inline void pgd_clear(pgd_t *pgdp) {} + +#define pte_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ + __FILE__, __LINE__, pte_val(e)) +#define pmd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ + __FILE__, __LINE__, pmd_val(e)) +#define pgd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ + __FILE__, __LINE__, pgd_val(e)) + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not... + * [we have the full set here even if they don't change from m68k] + */ +static inline int pte_read(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_READABLE; +} + +static inline int pte_write(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_WRITABLE; +} + +static inline int pte_exec(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_EXEC; +} + +static inline int pte_dirty(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_DIRTY; +} + +static inline int pte_young(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_ACCESSED; +} + +static inline int pte_file(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_FILE; +} + +static inline int pte_special(pte_t pte) +{ + return 0; +} + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_WRITABLE; + return pte; +} + +static inline pte_t pte_rdprotect(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_READABLE; + return pte; +} + +static inline pte_t pte_exprotect(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_EXEC; + return pte; +} + +static inline pte_t pte_mkclean(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_DIRTY; + return pte; +} + +static inline pte_t pte_mkold(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_ACCESSED; + return pte; +} + +static inline pte_t pte_mkwrite(pte_t pte) +{ + pte_val(pte) |= CF_PAGE_WRITABLE; + return pte; +} + +static inline pte_t pte_mkread(pte_t pte) +{ + pte_val(pte) |= CF_PAGE_READABLE; + return pte; +} + +static inline pte_t pte_mkexec(pte_t pte) +{ + pte_val(pte) |= CF_PAGE_EXEC; + return pte; +} + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte_val(pte) |= CF_PAGE_DIRTY; + return pte; +} + +static inline pte_t pte_mkyoung(pte_t pte) +{ + pte_val(pte) |= CF_PAGE_ACCESSED; + return pte; +} + +static inline pte_t pte_mknocache(pte_t pte) +{ + pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); + return pte; +} + +static inline pte_t pte_mkcache(pte_t pte) +{ + pte_val(pte) &= ~CF_PAGE_NOCACHE; + return pte; +} + +static inline pte_t pte_mkspecial(pte_t pte) +{ + return pte; +} + +#define swapper_pg_dir kernel_pg_dir +extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; + +/* + * Find an entry in a pagetable directory. + */ +#define pgd_index(address) ((address) >> PGDIR_SHIFT) +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) + +/* + * Find an entry in a kernel pagetable directory. + */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* + * Find an entry in the second-level pagetable. + */ +static inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address) +{ + return (pmd_t *) pgd; +} + +/* + * Find an entry in the third-level pagetable. + */ +#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) __pmd_page(*(dir)) + __pte_offset(address)) + +/* + * Disable caching for page at given kernel virtual address. + */ +static inline void nocache_page(void *vaddr) +{ + pgd_t *dir; + pmd_t *pmdp; + pte_t *ptep; + unsigned long addr = (unsigned long) vaddr; + + dir = pgd_offset_k(addr); + pmdp = pmd_offset(dir, addr); + ptep = pte_offset_kernel(pmdp, addr); + *ptep = pte_mknocache(*ptep); +} + +/* + * Enable caching for page at given kernel virtual address. + */ +static inline void cache_page(void *vaddr) +{ + pgd_t *dir; + pmd_t *pmdp; + pte_t *ptep; + unsigned long addr = (unsigned long) vaddr; + + dir = pgd_offset_k(addr); + pmdp = pmd_offset(dir, addr); + ptep = pte_offset_kernel(pmdp, addr); + *ptep = pte_mkcache(*ptep); +} + +#define PTE_FILE_MAX_BITS 21 +#define PTE_FILE_SHIFT 11 + +static inline unsigned long pte_to_pgoff(pte_t pte) +{ + return pte_val(pte) >> PTE_FILE_SHIFT; +} + +static inline pte_t pgoff_to_pte(unsigned pgoff) +{ + return __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE); +} + +/* + * Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) + */ +#define __swp_type(x) ((x).val & 0xFF) +#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT) +#define __swp_entry(typ, off) ((swp_entry_t) { (typ) | \ + (off << PTE_FILE_SHIFT) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) (__pte((x).val)) + +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) + +#define pte_offset_map(pmdp, addr) ((pte_t *)__pmd_page(*pmdp) + \ + __pte_offset(addr)) +#define pte_unmap(pte) ((void) 0) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) + +#endif /* !__ASSEMBLY__ */ +#endif /* _MCF_PGTABLE_H */ -- cgit v1.2.3 From 813db7fc1550687d3e42e793a67b2322df5114a4 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 14 Oct 2011 16:21:31 +1000 Subject: m68k: add page table size definitions for ColdFire V4e MMU Define the page table size and attributes for the ColdFire V4e MMU. Also setup the vmalloc and kmap regions we will use. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/pgtable_mm.h | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h index 87174c904d2b..dc35e0e106e4 100644 --- a/arch/m68k/include/asm/pgtable_mm.h +++ b/arch/m68k/include/asm/pgtable_mm.h @@ -40,6 +40,8 @@ /* PGDIR_SHIFT determines what a third-level page table entry can map */ #ifdef CONFIG_SUN3 #define PGDIR_SHIFT 17 +#elif defined(CONFIG_COLDFIRE) +#define PGDIR_SHIFT 22 #else #define PGDIR_SHIFT 25 #endif @@ -54,6 +56,10 @@ #define PTRS_PER_PTE 16 #define PTRS_PER_PMD 1 #define PTRS_PER_PGD 2048 +#elif defined(CONFIG_COLDFIRE) +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 1024 #else #define PTRS_PER_PTE 1024 #define PTRS_PER_PMD 8 @@ -66,12 +72,22 @@ #ifdef CONFIG_SUN3 #define KMAP_START 0x0DC00000 #define KMAP_END 0x0E000000 +#elif defined(CONFIG_COLDFIRE) +#define KMAP_START 0xe0000000 +#define KMAP_END 0xf0000000 #else #define KMAP_START 0xd0000000 #define KMAP_END 0xf0000000 #endif -#ifndef CONFIG_SUN3 +#ifdef CONFIG_SUN3 +extern unsigned long m68k_vmalloc_end; +#define VMALLOC_START 0x0f800000 +#define VMALLOC_END m68k_vmalloc_end +#elif defined(CONFIG_COLDFIRE) +#define VMALLOC_START 0xd0000000 +#define VMALLOC_END 0xe0000000 +#else /* Just any arbitrary offset to the start of the vmalloc VM area: the * current 8MB value just means that there will be a 8MB "hole" after the * physical memory until the kernel virtual memory starts. That means that @@ -82,11 +98,7 @@ #define VMALLOC_OFFSET (8*1024*1024) #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END KMAP_START -#else -extern unsigned long m68k_vmalloc_end; -#define VMALLOC_START 0x0f800000 -#define VMALLOC_END m68k_vmalloc_end -#endif /* CONFIG_SUN3 */ +#endif /* zero page used for uninitialized stuff */ extern void *empty_zero_page; @@ -130,6 +142,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, #ifdef CONFIG_SUN3 #include +#elif defined(CONFIG_COLDFIRE) +#include #else #include #endif @@ -138,6 +152,9 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, /* * Macro to mark a page protection value as "uncacheable". */ +#ifdef CONFIG_COLDFIRE +# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE)) +#else #ifdef SUN3_PAGE_NOCACHE # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE #else @@ -152,6 +169,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ : (prot))) +#endif /* CONFIG_COLDFIRE */ #include #endif /* !__ASSEMBLY__ */ -- cgit v1.2.3 From ae2eca724af2802739efe02b3fc56daa8b674eb9 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 14:38:09 +1000 Subject: m68k: add cache support for V4e ColdFire cores running with MMU enabled Add code to deal with instruction, data and branch caches of the V4e ColdFire cores when they are running with the MMU enabled. This code is loosely based on Freescales changes for the caches of the V4e ColdFire in the 2.6.25 kernel BSP. That code was originally by Kurt Mahan (now ). Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/cacheflush_mm.h | 88 +++++++++++++++++++++++++++++++++-- 1 file changed, 83 insertions(+), 5 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h index 73de7c89d8e0..8104bd874649 100644 --- a/arch/m68k/include/asm/cacheflush_mm.h +++ b/arch/m68k/include/asm/cacheflush_mm.h @@ -2,23 +2,89 @@ #define _M68K_CACHEFLUSH_H #include +#ifdef CONFIG_COLDFIRE +#include +#endif /* cache code */ #define FLUSH_I_AND_D (0x00000808) #define FLUSH_I (0x00000008) +#ifndef ICACHE_MAX_ADDR +#define ICACHE_MAX_ADDR 0 +#define ICACHE_SET_MASK 0 +#define DCACHE_MAX_ADDR 0 +#define DCACHE_SETMASK 0 +#endif + +static inline void flush_cf_icache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%ic,(%0)" + : "=a" (set) + : "a" (set)); + } +} + +static inline void flush_cf_dcache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%dc,(%0)" + : "=a" (set) + : "a" (set)); + } +} + +static inline void flush_cf_bcache(unsigned long start, unsigned long end) +{ + unsigned long set; + + for (set = start; set <= end; set += (0x10 - 3)) { + __asm__ __volatile__ ( + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)\n\t" + "addq%.l #1,%0\n\t" + "cpushl %%bc,(%0)" + : "=a" (set) + : "a" (set)); + } +} + /* * Cache handling functions */ static inline void flush_icache(void) { - if (CPU_IS_040_OR_060) + if (CPU_IS_COLDFIRE) { + flush_cf_icache(0, ICACHE_MAX_ADDR); + } else if (CPU_IS_040_OR_060) { asm volatile ( "nop\n" " .chip 68040\n" " cpusha %bc\n" " .chip 68k"); - else { + } else { unsigned long tmp; asm volatile ( "movec %%cacr,%0\n" " or.w %1,%0\n" @@ -51,12 +117,14 @@ extern void cache_push_v(unsigned long vaddr, int len); process changes. */ #define __flush_cache_all() \ ({ \ - if (CPU_IS_040_OR_060) \ + if (CPU_IS_COLDFIRE) { \ + flush_cf_dcache(0, DCACHE_MAX_ADDR); \ + } else if (CPU_IS_040_OR_060) { \ __asm__ __volatile__("nop\n\t" \ ".chip 68040\n\t" \ "cpusha %dc\n\t" \ ".chip 68k"); \ - else { \ + } else { \ unsigned long _tmp; \ __asm__ __volatile__("movec %%cacr,%0\n\t" \ "orw %1,%0\n\t" \ @@ -112,7 +180,17 @@ static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vm /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ static inline void __flush_page_to_ram(void *vaddr) { - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + unsigned long addr, start, end; + addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1); + start = addr & ICACHE_SET_MASK; + end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK; + if (start > end) { + flush_cf_bcache(0, end); + end = ICACHE_MAX_ADDR; + } + flush_cf_bcache(start, end); + } else if (CPU_IS_040_OR_060) { __asm__ __volatile__("nop\n\t" ".chip 68040\n\t" "cpushp %%bc,(%0)\n\t" -- cgit v1.2.3 From 0b0b808b50fd135c6bb22f773d216c3bcacb20d7 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 14:56:45 +1000 Subject: m68k: modify ColdFire 54xx cache support for MMU enabled Modify the cache setup for the ColdFire 54xx parts when running with the MMU enabled. We want to map the peripheral register space (MBAR region) as non cacheable. And create an identity mapping for all of RAM for the kernel. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/m54xxacr.h | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 16a1835f9b2a..47906aafbf67 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -39,8 +39,12 @@ #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ #define ACR_CM 0x00000060 /* Cache mode mask */ +#define ACR_SP 0x00000008 /* Supervisor protect */ #define ACR_WPROTECT 0x00000004 /* Write protect */ +#define ACR_BA(x) ((x) & 0xff000000) +#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) + #if defined(CONFIG_M5407) #define ICACHE_SIZE 0x4000 /* instruction - 16k */ @@ -56,6 +60,11 @@ #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ #define CACHE_WAYS 4 /* 4 ways */ +#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) +#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) +#define ICACHE_MAX_ADDR ICACHE_SET_MASK +#define DCACHE_MAX_ADDR DCACHE_SET_MASK + /* * Version 4 cores have a true harvard style separate instruction * and data cache. Enable data and instruction caches, also enable write @@ -73,6 +82,27 @@ #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif +#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) + +#if defined(CONFIG_MMU) +/* + * If running with the MMU enabled then we need to map the internal + * register region as non-cacheable. And then we map all our RAM as + * cacheable and supervisor access only. + */ +#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ + ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ + ACR_ENABLE+ACR_SUPER+ACR_SP) +#define ACR2_MODE 0 +#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ + ACR_ENABLE+ACR_SUPER+ACR_SP) + +#else + +/* + * For the non-MMU enabled case we map all of RAM as cacheable. + */ #if defined(CONFIG_CACHE_COPYBACK) #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) #else @@ -80,7 +110,6 @@ #endif #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) -#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) @@ -94,4 +123,5 @@ #define CACHE_PUSH #endif +#endif /* CONFIG_MMU */ #endif /* m54xxacr_h */ -- cgit v1.2.3 From b852de4e7f7d6f4373901e3a880f6f29a65e7937 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 15:09:44 +1000 Subject: m68k: add TLB flush support for the ColdFire V4e MMU hardware The ColdFire V4e MMU is unlike any of the other m68k MMU hardware. It needs its own TLB flush support code. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/tlbflush.h | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/tlbflush.h b/arch/m68k/include/asm/tlbflush.h index a6b4ed4fc90f..965ea35c9a40 100644 --- a/arch/m68k/include/asm/tlbflush.h +++ b/arch/m68k/include/asm/tlbflush.h @@ -5,10 +5,13 @@ #ifndef CONFIG_SUN3 #include +#include static inline void flush_tlb_kernel_page(void *addr) { - if (CPU_IS_040_OR_060) { + if (CPU_IS_COLDFIRE) { + mmu_write(MMUOR, MMUOR_CNL); + } else if (CPU_IS_040_OR_060) { mm_segment_t old_fs = get_fs(); set_fs(KERNEL_DS); __asm__ __volatile__(".chip 68040\n\t" @@ -25,12 +28,15 @@ static inline void flush_tlb_kernel_page(void *addr) */ static inline void __flush_tlb(void) { - if (CPU_IS_040_OR_060) + if (CPU_IS_COLDFIRE) { + mmu_write(MMUOR, MMUOR_CNL); + } else if (CPU_IS_040_OR_060) { __asm__ __volatile__(".chip 68040\n\t" "pflushan\n\t" ".chip 68k"); - else if (CPU_IS_020_OR_030) + } else if (CPU_IS_020_OR_030) { __asm__ __volatile__("pflush #0,#4"); + } } static inline void __flush_tlb040_one(unsigned long addr) @@ -43,7 +49,9 @@ static inline void __flush_tlb040_one(unsigned long addr) static inline void __flush_tlb_one(unsigned long addr) { - if (CPU_IS_040_OR_060) + if (CPU_IS_COLDFIRE) + mmu_write(MMUOR, MMUOR_CNL); + else if (CPU_IS_040_OR_060) __flush_tlb040_one(addr); else if (CPU_IS_020_OR_030) __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr)); @@ -56,12 +64,15 @@ static inline void __flush_tlb_one(unsigned long addr) */ static inline void flush_tlb_all(void) { - if (CPU_IS_040_OR_060) + if (CPU_IS_COLDFIRE) { + mmu_write(MMUOR, MMUOR_CNL); + } else if (CPU_IS_040_OR_060) { __asm__ __volatile__(".chip 68040\n\t" "pflusha\n\t" ".chip 68k"); - else if (CPU_IS_020_OR_030) + } else if (CPU_IS_020_OR_030) { __asm__ __volatile__("pflusha"); + } } static inline void flush_tlb_mm(struct mm_struct *mm) -- cgit v1.2.3 From bfe4375a1a184c2145ef235e782660400b005882 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 15 Nov 2011 14:12:01 +1000 Subject: m68k: define PAGE_OFFSET_RAW for ColdFire CPU with MMU enabled The ColdFire CPU configurations need PAGE_OFFSET_RAW set to the base of their RAM. It doesn't matter if they are running with the MMU enabled or disabled, it is always set to the base of RAM. We can keep the choices simple here and key of CONFIG_RAMBASE. If it is defined we are on a plaftorm (ColdFire or other non-MMU systems) which have a configurable RAM base, just use it. Reported-by: Alexander Stein Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/page_offset.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/page_offset.h b/arch/m68k/include/asm/page_offset.h index 1780152d81da..82626a8f1d0a 100644 --- a/arch/m68k/include/asm/page_offset.h +++ b/arch/m68k/include/asm/page_offset.h @@ -1,11 +1,9 @@ /* This handles the memory map.. */ -#ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 -#define PAGE_OFFSET_RAW 0x00000000 -#else +#if defined(CONFIG_RAMBASE) +#define PAGE_OFFSET_RAW CONFIG_RAMBASE +#elif defined(CONFIG_SUN3) #define PAGE_OFFSET_RAW 0x0E000000 -#endif #else -#define PAGE_OFFSET_RAW CONFIG_RAMBASE +#define PAGE_OFFSET_RAW 0x00000000 #endif -- cgit v1.2.3 From 9e95f7cdf5c3741ed00a298c0201d624833b4102 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 17 Oct 2011 17:26:11 +1000 Subject: m68k: set ColdFire MMU page size We use the ColdFire V4e MMU page size of 8KiB. Define PAGE_SHIFT appropriately. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/page.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h index ba6c91d5f3a9..98baa82a8615 100644 --- a/arch/m68k/include/asm/page.h +++ b/arch/m68k/include/asm/page.h @@ -6,10 +6,10 @@ #include /* PAGE_SHIFT determines the page size */ -#ifndef CONFIG_SUN3 -#define PAGE_SHIFT (12) +#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) +#define PAGE_SHIFT 13 #else -#define PAGE_SHIFT (13) +#define PAGE_SHIFT 12 #endif #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -- cgit v1.2.3 From 33d4bcca603c9174c0ee0e312fd3c6da03ff9e15 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 28 Oct 2011 16:59:50 +1000 Subject: m68k: MMU enabled ColdFire needs 8k ELF alignment Like the SUN3 hardware MMU the ColdFire MMU uses 8k pages. So we want our ELF page size alingment to also be 8k. Modify the ELF alignment setting. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/elf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h index 01c193d91412..e9b7cda59744 100644 --- a/arch/m68k/include/asm/elf.h +++ b/arch/m68k/include/asm/elf.h @@ -59,10 +59,10 @@ typedef struct user_m68kfp_struct elf_fpregset_t; is actually used on ASV. */ #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 -#ifndef CONFIG_SUN3 -#define ELF_EXEC_PAGESIZE 4096 -#else +#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) #define ELF_EXEC_PAGESIZE 8192 +#else +#define ELF_EXEC_PAGESIZE 4096 #endif /* This is the location that an ET_DYN program is loaded if exec'ed. Typical -- cgit v1.2.3 From 83b73d6cb8301df32d9887c16c83490c4fd1f55f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Oct 2011 15:07:29 +1000 Subject: m68k: ColdFire V4e MMU context support code Add code to manage the context's of the ColdFire V4e MMU. This code is mostly taken from the Freescale 2.6.35 kernel BSP for MMU enabled ColdFire. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/atomic.h | 10 ++ arch/m68k/include/asm/mmu_context.h | 250 +++++++++++++++++++++++++++++------- 2 files changed, 211 insertions(+), 49 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index 65c6be6c8180..4eba796c00d4 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -55,6 +55,16 @@ static inline int atomic_dec_and_test(atomic_t *v) return c != 0; } +static inline int atomic_dec_and_test_lt(atomic_t *v) +{ + char c; + __asm__ __volatile__( + "subql #1,%1; slt %0" + : "=d" (c), "=m" (*v) + : "m" (*v)); + return c != 0; +} + static inline int atomic_inc_and_test(atomic_t *v) { char c; diff --git a/arch/m68k/include/asm/mmu_context.h b/arch/m68k/include/asm/mmu_context.h index 7d4341e55a99..dc3be991d634 100644 --- a/arch/m68k/include/asm/mmu_context.h +++ b/arch/m68k/include/asm/mmu_context.h @@ -8,7 +8,206 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) } #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 + +#if defined(CONFIG_COLDFIRE) + +#include +#include +#include +#include + +#define NO_CONTEXT 256 +#define LAST_CONTEXT 255 +#define FIRST_CONTEXT 1 + +extern unsigned long context_map[]; +extern mm_context_t next_mmu_context; + +extern atomic_t nr_free_contexts; +extern struct mm_struct *context_mm[LAST_CONTEXT+1]; +extern void steal_context(void); + +static inline void get_mmu_context(struct mm_struct *mm) +{ + mm_context_t ctx; + + if (mm->context != NO_CONTEXT) + return; + while (atomic_dec_and_test_lt(&nr_free_contexts)) { + atomic_inc(&nr_free_contexts); + steal_context(); + } + ctx = next_mmu_context; + while (test_and_set_bit(ctx, context_map)) { + ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); + if (ctx > LAST_CONTEXT) + ctx = 0; + } + next_mmu_context = (ctx + 1) & LAST_CONTEXT; + mm->context = ctx; + context_mm[ctx] = mm; +} + +/* + * Set up the context for a new address space. + */ +#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0) + +/* + * We're finished using the context for an address space. + */ +static inline void destroy_context(struct mm_struct *mm) +{ + if (mm->context != NO_CONTEXT) { + clear_bit(mm->context, context_map); + mm->context = NO_CONTEXT; + atomic_inc(&nr_free_contexts); + } +} + +static inline void set_context(mm_context_t context, pgd_t *pgd) +{ + __asm__ __volatile__ ("movec %0,%%asid" : : "d" (context)); +} + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + get_mmu_context(tsk->mm); + set_context(tsk->mm->context, next->pgd); +} + +/* + * After we have set current->mm to a new value, this activates + * the context for the new mm so we see the new mappings. + */ +static inline void activate_mm(struct mm_struct *active_mm, + struct mm_struct *mm) +{ + get_mmu_context(mm); + set_context(mm->context, mm->pgd); +} + +#define deactivate_mm(tsk, mm) do { } while (0) + +extern void mmu_context_init(void); +#define prepare_arch_switch(next) load_ksp_mmu(next) + +static inline void load_ksp_mmu(struct task_struct *task) +{ + unsigned long flags; + struct mm_struct *mm; + int asid; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + unsigned long mmuar; + + local_irq_save(flags); + mmuar = task->thread.ksp; + + /* Search for a valid TLB entry, if one is found, don't remap */ + mmu_write(MMUAR, mmuar); + mmu_write(MMUOR, MMUOR_STLB | MMUOR_ADR); + if (mmu_read(MMUSR) & MMUSR_HIT) + goto end; + + if (mmuar >= PAGE_OFFSET) { + mm = &init_mm; + } else { + pr_info("load_ksp_mmu: non-kernel mm found: 0x%p\n", task->mm); + mm = task->mm; + } + + if (!mm) + goto bug; + + pgd = pgd_offset(mm, mmuar); + if (pgd_none(*pgd)) + goto bug; + + pmd = pmd_offset(pgd, mmuar); + if (pmd_none(*pmd)) + goto bug; + + pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar) + : pte_offset_map(pmd, mmuar); + if (pte_none(*pte) || !pte_present(*pte)) + goto bug; + + set_pte(pte, pte_mkyoung(*pte)); + asid = mm->context & 0xff; + if (!pte_dirty(*pte) && mmuar <= PAGE_OFFSET) + set_pte(pte, pte_wrprotect(*pte)); + + mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) | + (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK) + >> CF_PAGE_MMUTR_SHIFT) | MMUTR_V); + + mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) | + ((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X); + + mmu_write(MMUOR, MMUOR_ACC | MMUOR_UAA); + + goto end; + +bug: + pr_info("ksp load failed: mm=0x%p ksp=0x08%lx\n", mm, mmuar); +end: + local_irq_restore(flags); +} + +#elif defined(CONFIG_SUN3) +#include +#include + +extern unsigned long get_free_context(struct mm_struct *mm); +extern void clear_context(unsigned long context); + +/* set the context for a new task to unmapped */ +static inline int init_new_context(struct task_struct *tsk, + struct mm_struct *mm) +{ + mm->context = SUN3_INVALID_CONTEXT; + return 0; +} + +/* find the context given to this process, and if it hasn't already + got one, go get one for it. */ +static inline void get_mmu_context(struct mm_struct *mm) +{ + if (mm->context == SUN3_INVALID_CONTEXT) + mm->context = get_free_context(mm); +} + +/* flush context if allocated... */ +static inline void destroy_context(struct mm_struct *mm) +{ + if (mm->context != SUN3_INVALID_CONTEXT) + clear_context(mm->context); +} + +static inline void activate_context(struct mm_struct *mm) +{ + get_mmu_context(mm); + sun3_put_context(mm->context); +} + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + activate_context(tsk->mm); +} + +#define deactivate_mm(tsk, mm) do { } while (0) + +static inline void activate_mm(struct mm_struct *prev_mm, + struct mm_struct *next_mm) +{ + activate_context(next_mm); +} + +#else #include #include @@ -103,55 +302,8 @@ static inline void activate_mm(struct mm_struct *prev_mm, switch_mm_0460(next_mm); } -#else /* CONFIG_SUN3 */ -#include -#include - -extern unsigned long get_free_context(struct mm_struct *mm); -extern void clear_context(unsigned long context); - -/* set the context for a new task to unmapped */ -static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - mm->context = SUN3_INVALID_CONTEXT; - return 0; -} - -/* find the context given to this process, and if it hasn't already - got one, go get one for it. */ -static inline void get_mmu_context(struct mm_struct *mm) -{ - if(mm->context == SUN3_INVALID_CONTEXT) - mm->context = get_free_context(mm); -} - -/* flush context if allocated... */ -static inline void destroy_context(struct mm_struct *mm) -{ - if(mm->context != SUN3_INVALID_CONTEXT) - clear_context(mm->context); -} - -static inline void activate_context(struct mm_struct *mm) -{ - get_mmu_context(mm); - sun3_put_context(mm->context); -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) -{ - activate_context(tsk->mm); -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -static inline void activate_mm(struct mm_struct *prev_mm, - struct mm_struct *next_mm) -{ - activate_context(next_mm); -} - #endif + #else /* !CONFIG_MMU */ static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) -- cgit v1.2.3 From d49316e84bbad307543c50be53555ca9a768f31d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Oct 2011 16:16:43 +1000 Subject: m68k: use ColdFire MMU read/write bit flags when ioremapping The ColdFire MMU has separate read and write bits, unlike the Motorola m68k MMU which has a single read-only bit. Define a _PAGE_READWRITE value for the Motorola MMU, which is 0, so we can unconditionaly include that in the page table entry bits when setting up ioremapped pages. Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/motorola_pgtable.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h index 45bd3f589bf0..e0fdd4d08075 100644 --- a/arch/m68k/include/asm/motorola_pgtable.h +++ b/arch/m68k/include/asm/motorola_pgtable.h @@ -8,6 +8,7 @@ #define _PAGE_PRESENT 0x001 #define _PAGE_SHORT 0x002 #define _PAGE_RONLY 0x004 +#define _PAGE_READWRITE 0x000 #define _PAGE_ACCESSED 0x008 #define _PAGE_DIRTY 0x010 #define _PAGE_SUPER 0x080 /* 68040 supervisor only */ -- cgit v1.2.3 From 066bf87b5c1b87f2eba7880b125f88e4f67e1c16 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Oct 2011 16:24:19 +1000 Subject: m68k: ColdFire V4e MMU paging init code and miss handler The different ColdFire V4e MMU requires its own dedicated paging init code, and a TLB miss handler for its software driven TLB. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/mcfmmu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/mcfmmu.h b/arch/m68k/include/asm/mcfmmu.h index 8fdcfedd5d15..26cc3d5a63f8 100644 --- a/arch/m68k/include/asm/mcfmmu.h +++ b/arch/m68k/include/asm/mcfmmu.h @@ -105,6 +105,8 @@ static inline void mmu_write(u32 a, u32 v) __asm__ __volatile__ ("nop"); } +int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word); + #endif #endif /* MCFMMU_H */ -- cgit v1.2.3 From 74d4799221d0f5c5997a8b9817fe1ec76de0a666 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 18 Oct 2011 16:52:41 +1000 Subject: m68k: create ColdFire MMU pgalloc code Add code to support the ColdFire V4e MMU pgalloc functions. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/mcf_pgalloc.h | 102 ++++++++++++++++++++++++++++++++++++ arch/m68k/include/asm/pgalloc.h | 4 +- 2 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 arch/m68k/include/asm/mcf_pgalloc.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/mcf_pgalloc.h b/arch/m68k/include/asm/mcf_pgalloc.h new file mode 100644 index 000000000000..313f3dd23cdc --- /dev/null +++ b/arch/m68k/include/asm/mcf_pgalloc.h @@ -0,0 +1,102 @@ +#ifndef M68K_MCF_PGALLOC_H +#define M68K_MCF_PGALLOC_H + +#include +#include + +extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_page((unsigned long) pte); +} + +extern const char bad_pmd_string[]; + +extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) +{ + unsigned long page = __get_free_page(GFP_DMA|__GFP_REPEAT); + + if (!page) + return NULL; + + memset((void *)page, 0, PAGE_SIZE); + return (pte_t *) (page); +} + +extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address) +{ + return (pmd_t *) pgd; +} + +#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); }) +#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) + +#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr) + +#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \ + (unsigned long)(page_address(page))) + +#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte)) + +#define pmd_pgtable(pmd) pmd_page(pmd) + +static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page, + unsigned long address) +{ + __free_page(page); +} + +#define __pmd_free_tlb(tlb, pmd, address) do { } while (0) + +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long address) +{ + struct page *page = alloc_pages(GFP_DMA|__GFP_REPEAT, 0); + pte_t *pte; + + if (!page) + return NULL; + + pte = kmap(page); + if (pte) { + clear_page(pte); + __flush_page_to_ram(pte); + flush_tlb_kernel_page(pte); + nocache_page(pte); + } + kunmap(page); + + return page; +} + +extern inline void pte_free(struct mm_struct *mm, struct page *page) +{ + __free_page(page); +} + +/* + * In our implementation, each pgd entry contains 1 pmd that is never allocated + * or freed. pgd_present is always 1, so this should never be called. -NL + */ +#define pmd_free(mm, pmd) BUG() + +static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + free_page((unsigned long) pgd); +} + +static inline pgd_t *pgd_alloc(struct mm_struct *mm) +{ + pgd_t *new_pgd; + + new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN); + if (!new_pgd) + return NULL; + memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE); + memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT); + return new_pgd; +} + +#define pgd_populate(mm, pmd, pte) BUG() + +#endif /* M68K_MCF_PGALLOC_H */ diff --git a/arch/m68k/include/asm/pgalloc.h b/arch/m68k/include/asm/pgalloc.h index c294aad8a900..37bee7e3223d 100644 --- a/arch/m68k/include/asm/pgalloc.h +++ b/arch/m68k/include/asm/pgalloc.h @@ -7,7 +7,9 @@ #ifdef CONFIG_MMU #include -#ifdef CONFIG_SUN3 +#if defined(CONFIG_COLDFIRE) +#include +#elif defined(CONFIG_SUN3) #include #else #include -- cgit v1.2.3 From 0a2796da1182a7dcfba41f796f45986237bc1688 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 19 Oct 2011 14:10:03 +1000 Subject: m68k: add ColdFire FPU support for the V4e ColdFire CPUs The V4e ColdFire CPU family also has an integrated FPU (as well as the MMU). So add code to support this hardware along side the existing m68k FPU code. The ColdFire FPU is of course different to all previous 68k FP units. It is close in operation to the 68060, but not completely compatible. The biggest issue to deal with is that the ColdFire FPU multi-move instructions are different. It does not support multi-moving the FP control registers, and the multi-move of the FP data registers uses a different instruction mnemonic. Signed-off-by: Greg Ungerer Acked-by: Matt Waddel Acked-by: Kurt Mahan --- arch/m68k/include/asm/fpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/fpu.h b/arch/m68k/include/asm/fpu.h index ffb6b8cfc6d5..526db9da9e43 100644 --- a/arch/m68k/include/asm/fpu.h +++ b/arch/m68k/include/asm/fpu.h @@ -12,6 +12,8 @@ #define FPSTATESIZE (96) #elif defined(CONFIG_M68KFPU_EMU) #define FPSTATESIZE (28) +#elif defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU) +#define FPSTATESIZE (16) #elif defined(CONFIG_M68060) #define FPSTATESIZE (12) #else -- cgit v1.2.3