From 571f0608e1a53d6d405c385cc9c11b7902b35b7f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 5 Mar 2011 23:50:37 +1000 Subject: m68knommu: remove MBAR and IPSBAR hacks for the ColdFire 520x CPUs The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses. They do not use the setable peripheral address registers like the MBAR and IPSBAR used on many other ColdFire parts. Don't use fake values of MBAR and IPSBAR when using peripheral addresses for them, there is no need to. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/coldfire/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/m68knommu/platform/coldfire/head.S') diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index d5977909ae5f..7967e8ab9fae 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -68,14 +68,14 @@ #elif defined(CONFIG_M520x) .macro GET_MEM_SIZE clrl %d0 - movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ + movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ andl #0x1f, %d2 /* Get only the chip select size */ beq 3f /* Check if it is enabled */ addql #1, %d2 /* Form exponent */ moveql #1, %d0 lsll %d2, %d0 /* 2 ^ exponent */ 3: - movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ + movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ andl #0x1f, %d2 /* Get only the chip select size */ beq 4f /* Check if it is enabled */ addql #1, %d2 /* Form exponent */ -- cgit v1.2.3 From 6a92e1982d5c538d1cfafbe4b0cb16d49306854f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sun, 6 Mar 2011 23:01:46 +1000 Subject: m68knommu: clean up use of MBAR for DRAM registers on ColdFire start In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/coldfire/head.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/m68knommu/platform/coldfire/head.S') diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 7967e8ab9fae..129bff4956b5 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -41,17 +41,17 @@ * DRAM controller is quite different. */ .macro GET_MEM_SIZE - movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */ + movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ btst #0,%d0 /* check if region enabled */ beq 1f andl #0xfffc0000,%d0 beq 1f addl #0x00040000,%d0 /* convert mask to size */ 1: - movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ + movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ btst #0,%d1 /* check if region enabled */ beq 2f - andl #0xfffc0000, %d1 + andl #0xfffc0000,%d1 beq 2f addl #0x00040000,%d1 addl %d1,%d0 /* total mem size in d0 */ -- cgit v1.2.3