From f1a59d244abd8d7b94b90f45ee5e0988e5a154cb Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 6 May 2009 11:36:00 +1000 Subject: m68knommu: remove interrupt masking from ColdFire pit timer With proper interrupt controller code in place there is no need for devices like the timers to have custom interrupt masking code. Remove it (and the defines that go along with it). Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/coldfire/pit.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/m68knommu') diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c index 61b96211f8ff..d8720ee34510 100644 --- a/arch/m68knommu/platform/coldfire/pit.c +++ b/arch/m68knommu/platform/coldfire/pit.c @@ -32,7 +32,6 @@ */ #define FREQ ((MCF_CLK / 2) / 64) #define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) -#define INTC0 (MCF_IPSBAR + MCFICM_INTC0) #define PIT_CYCLES_PER_JIFFY (FREQ / HZ) static u32 pit_cnt; @@ -154,8 +153,6 @@ static struct clocksource pit_clk = { void hw_timer_init(void) { - u32 imr; - cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); cf_pit_clockevent.max_delta_ns = @@ -166,11 +163,6 @@ void hw_timer_init(void) setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); - __raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1); - imr = __raw_readl(INTC0 + MCFPIT_IMR); - imr &= ~MCFPIT_IMR_IBIT; - __raw_writel(imr, INTC0 + MCFPIT_IMR); - pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); clocksource_register(&pit_clk); } -- cgit v1.2.3