From 1584d7f2d58999c00066a4afc4ad95e07b2a04e8 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 7 Oct 2010 16:03:43 -0700 Subject: MIPS: Add identifiers for Octeon II CPUs. Signed-off-by: David Daney Patchwork: http://patchwork.linux-mips.org/patch/1662/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/include/asm/cpu.h') diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index b201a8f5b127..049a189ea91f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -131,6 +131,7 @@ #define PRID_IMP_CAVIUM_CN56XX 0x0400 #define PRID_IMP_CAVIUM_CN50XX 0x0600 #define PRID_IMP_CAVIUM_CN52XX 0x0700 +#define PRID_IMP_CAVIUM_CN63XX 0x9000 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC @@ -231,7 +232,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, CPU_LAST }; -- cgit v1.2.3 From 602977b0d672687909b0cb0542ede134ed6ef858 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Sat, 16 Oct 2010 14:22:30 -0700 Subject: MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by: Kevin Cernekee Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/1706/ Signed-off-by: Ralf Baechle