From e9f4a6b3421e936c3ee9d74710243897d74dbaa2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Wed, 11 Jun 2025 13:28:26 +0200 Subject: MIPS: Don't crash in stack_top() for tasks without ABI or vDSO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not all tasks have an ABI associated or vDSO mapped, for example kthreads never do. If such a task ever ends up calling stack_top(), it will derefence the NULL ABI pointer and crash. This can for example happen when using kunit: mips_stack_top+0x28/0xc0 arch_pick_mmap_layout+0x190/0x220 kunit_vm_mmap_init+0xf8/0x138 __kunit_add_resource+0x40/0xa8 kunit_vm_mmap+0x88/0xd8 usercopy_test_init+0xb8/0x240 kunit_try_run_case+0x5c/0x1a8 kunit_generic_run_threadfn_adapter+0x28/0x50 kthread+0x118/0x240 ret_from_kernel_thread+0x14/0x1c Only dereference the ABI point if it is set. The GIC page is also included as it is specific to the vDSO. Also move the randomization adjustment into the same conditional. Signed-off-by: Thomas Weißschuh Reviewed-by: David Gow Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index b630604c577f..02aa6a04a21d 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -690,18 +690,20 @@ unsigned long mips_stack_top(void) } /* Space for the VDSO, data page & GIC user page */ - top -= PAGE_ALIGN(current->thread.abi->vdso->size); - top -= PAGE_SIZE; - top -= mips_gic_present() ? PAGE_SIZE : 0; + if (current->thread.abi) { + top -= PAGE_ALIGN(current->thread.abi->vdso->size); + top -= PAGE_SIZE; + top -= mips_gic_present() ? PAGE_SIZE : 0; + + /* Space to randomize the VDSO base */ + if (current->flags & PF_RANDOMIZE) + top -= VDSO_RANDOMIZE_SIZE; + } /* Space for cache colour alignment */ if (cpu_has_dc_aliases) top -= shm_align_mask + 1; - /* Space to randomize the VDSO base */ - if (current->flags & PF_RANDOMIZE) - top -= VDSO_RANDOMIZE_SIZE; - return top; } -- cgit v1.2.3 From 07f8888ee7df5189e64839abb26842dc6c2da371 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 10 Jul 2025 16:54:42 +0200 Subject: MIPS: disable MMID when not supported by the hardware It is possible that MMID is supported at the CPU level, but its integration in a SoC prevents its usage. For instance, if the System-level Interconnect (also known as Network on Chip) does not support global invalidation, then the MMID feature is not usable. The current implementation of MMID relies on the GINV* instructions. This patch allows the disabling of MMID based on a device tree property, as this issue cannot be detected at runtime. MMID is set up very early during the boot process, even before device tree data can be accessed. Therefore, when we determine whether MMID needs to be disabled, some MMID setup has already been performed for the boot CPU. Consequently, we must revert the MMID setup on the first CPU before disabling the feature for the subsequent CPUs that will be initialized later. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cpu-probe.c | 42 ++++++++++++++++++++++++++++++++++++++++-- arch/mips/kernel/mips-cm.c | 5 +++++ 2 files changed, 45 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index af7412549e6e..04dc9ab55524 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -9,6 +9,7 @@ */ #include #include +#include #include #include #include @@ -37,6 +38,8 @@ unsigned int elf_hwcap __read_mostly; EXPORT_SYMBOL_GPL(elf_hwcap); +static bool mmid_disabled_quirk; + static inline unsigned long cpu_get_msa_id(void) { unsigned long status, msa_id; @@ -645,7 +648,7 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c) config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); if (cpu_has_mips_r6) { - if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid) + if (!mmid_disabled_quirk && (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)) config5 |= MIPS_CONF5_MI; else config5 &= ~MIPS_CONF5_MI; @@ -708,7 +711,6 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c) max_mmid_width); asid_mask = GENMASK(max_mmid_width - 1, 0); } - set_cpu_asid_mask(c, asid_mask); } } @@ -2046,3 +2048,39 @@ void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; } + +void cpu_disable_mmid(void) +{ + int i; + unsigned long asid_mask; + unsigned int cpu = smp_processor_id(); + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config4 = read_c0_config4(); + unsigned int config5 = read_c0_config5(); + + /* Setup the initial ASID mask based on config4 */ + asid_mask = MIPS_ENTRYHI_ASID; + if (config4 & MIPS_CONF4_AE) + asid_mask |= MIPS_ENTRYHI_ASIDX; + set_cpu_asid_mask(c, asid_mask); + + /* Disable MMID in the C0 and update cpuinfo_mips accordingly */ + config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); + config5 &= ~MIPS_CONF5_MI; + write_c0_config5(config5); + /* Ensure the write to config5 above takes effect */ + back_to_back_c0_hazard(); + c->options &= ~MIPS_CPU_MMID; + + /* Setup asid cache value cleared in per_cpu_trap_init() */ + cpu_data[cpu].asid_cache = asid_first_version(cpu); + + /* Reinit context for each CPU */ + for_each_possible_cpu(i) + set_cpu_context(i, &init_mm, 0); + + /* Ensure that now MMID will be seen as disable */ + mmid_disabled_quirk = true; + + pr_info("MMID support disabled due to hardware support issue\n"); +} diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 43cb1e20baed..96c607dbb3a0 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -248,6 +248,11 @@ void mips_cm_update_property(void) return; pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken"); mips_cm_is_l2_hci_broken = true; + + /* Disable MMID only if it was configured */ + if (cpu_has_mmid) + cpu_disable_mmid(); + of_node_put(cm_node); } -- cgit v1.2.3 From c71085f2c0f18f025784ce975358adcccaa8c041 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 11 Jul 2025 11:54:20 +0200 Subject: MIPS: CPS: Improve mips_cps_first_online_in_cluster() The initial implementation of this function goes through all the CPUs in a cluster to determine if the current CPU is the only one running. This process occurs every time the function is called. However, during boot, we already perform this task, so let's take advantage of this opportunity to create and fill a CPU bitmask that can be easily and efficiently used later. This patch modifies the function to allow providing the first available online CPU when one already exists, which is necessary for delay CPU calibration optimization. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/mips-cm.c | 47 ++++++++++++++++------------------------------ arch/mips/kernel/smp-cps.c | 5 ++++- 2 files changed, 20 insertions(+), 32 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 96c607dbb3a0..7c9c5dc38823 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -10,6 +10,7 @@ #include #include +#include #include void __iomem *mips_gcr_base; @@ -534,39 +535,23 @@ void mips_cm_error_report(void) write_gcr_error_cause(cm_error); } -unsigned int mips_cps_first_online_in_cluster(void) +unsigned int mips_cps_first_online_in_cluster(int *first_cpu) { - unsigned int local_cl; - int i; - - local_cl = cpu_cluster(¤t_cpu_data); + unsigned int local_cl = cpu_cluster(¤t_cpu_data); + struct cpumask *local_cl_mask; /* - * We rely upon knowledge that CPUs are numbered sequentially by - * cluster - ie. CPUs 0..X will be in cluster 0, CPUs X+1..Y in cluster - * 1, CPUs Y+1..Z in cluster 2 etc. This means that CPUs in the same - * cluster will immediately precede or follow one another. - * - * First we scan backwards, until we find an online CPU in the cluster - * or we move on to another cluster. + * mips_cps_cluster_bootcfg is allocated in cps_prepare_cpus. If it is + * not yet done, then we are so early that only one CPU is running, so + * it is the first online CPU in the cluster. */ - for (i = smp_processor_id() - 1; i >= 0; i--) { - if (cpu_cluster(&cpu_data[i]) != local_cl) - break; - if (!cpu_online(i)) - continue; - return false; - } - - /* Then do the same for higher numbered CPUs */ - for (i = smp_processor_id() + 1; i < nr_cpu_ids; i++) { - if (cpu_cluster(&cpu_data[i]) != local_cl) - break; - if (!cpu_online(i)) - continue; - return false; - } - - /* We found no online CPUs in the local cluster */ - return true; + if (IS_ENABLED(CONFIG_MIPS_CPS) && mips_cps_cluster_bootcfg) + local_cl_mask = &mips_cps_cluster_bootcfg[local_cl].cpumask; + else + return true; + + *first_cpu = cpumask_any_and_but(local_cl_mask, + cpu_online_mask, + smp_processor_id()); + return (*first_cpu >= nr_cpu_ids); } diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 7b0e69af4097..6c5f15293a8e 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -283,7 +283,7 @@ static void __init cps_smp_setup(void) static void __init cps_prepare_cpus(unsigned int max_cpus) { - unsigned int nclusters, ncores, core_vpes, c, cl, cca; + unsigned int nclusters, ncores, core_vpes, nvpe = 0, c, cl, cca; bool cca_unsuitable, cores_limited; struct cluster_boot_config *cluster_bootcfg; struct core_boot_config *core_bootcfg; @@ -356,10 +356,13 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) /* Allocate VPE boot configuration structs */ for (c = 0; c < ncores; c++) { + int v; core_vpes = core_vpe_count(cl, c); core_bootcfg[c].vpe_config = kcalloc(core_vpes, sizeof(*core_bootcfg[c].vpe_config), GFP_KERNEL); + for (v = 0; v < core_vpes; v++) + cpumask_set_cpu(nvpe++, &mips_cps_cluster_bootcfg[cl].cpumask); if (!core_bootcfg[c].vpe_config) goto err_out; } -- cgit v1.2.3 From db6f8fcd56438a078ef61779ff68068a0886a79b Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 11 Jul 2025 11:54:21 +0200 Subject: MIPS: CPS: Optimise delay CPU calibration for SMP On MIPS architecture with CPS-based SMP support, all CPU cores in the same cluster run at the same frequency since they share the same L2 cache, requiring a fixed CPU/L2 cache ratio. This allows to implement calibrate_delay_is_known(), which will return 0 (triggering calibration) only for the primary CPU of each cluster. For other CPUs, we can simply reuse the value from their cluster's primary CPU core. With the introduction of this patch, a configuration running 32 cores spread across two clusters sees a significant reduction in boot time by approximately 600 milliseconds. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/smp-cps.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 6c5f15293a8e..22d4f9ff3ae2 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -281,6 +281,17 @@ static void __init cps_smp_setup(void) #endif /* CONFIG_MIPS_MT_FPAFF */ } +unsigned long calibrate_delay_is_known(void) +{ + int first_cpu_cluster = 0; + + /* The calibration has to be done on the primary CPU of the cluster */ + if (mips_cps_first_online_in_cluster(&first_cpu_cluster)) + return 0; + + return cpu_data[first_cpu_cluster].udelay_val; +} + static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned int nclusters, ncores, core_vpes, nvpe = 0, c, cl, cca; -- cgit v1.2.3 From 3ebcbf079c26ab6e82faa7f896b66def55547eee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Fri, 18 Jul 2025 15:18:24 +0200 Subject: MIPS: Don't use %pK through printk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Restricted pointers ("%pK") are not meant to be used through printk(). It can unintentionally expose security sensitive, raw pointer values. Use regular pointer formatting instead. Link: https://lore.kernel.org/lkml/20250113171731-dc10e3c1-da64-4af0-b767-7c7070468023@linutronix.de/ Signed-off-by: Thomas Weißschuh Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/relocate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/mips/kernel') diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index cda7983e7c18..7f1c136ad850 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -138,7 +138,7 @@ static int __init reloc_handler(u32 type, u32 *loc_orig, u32 *loc_new, apply_r_mips_hi16_rel(loc_orig, loc_new, offset); break; default: - pr_err("Unhandled relocation type %d at 0x%pK\n", type, + pr_err("Unhandled relocation type %d at 0x%p\n", type, loc_orig); return -ENOEXEC; } @@ -439,10 +439,10 @@ static void show_kernel_relocation(const char *level) { if (__kaslr_offset > 0) { printk(level); - pr_cont("Kernel relocated by 0x%pK\n", (void *)__kaslr_offset); - pr_cont(" .text @ 0x%pK\n", _text); - pr_cont(" .data @ 0x%pK\n", _sdata); - pr_cont(" .bss @ 0x%pK\n", __bss_start); + pr_cont("Kernel relocated by 0x%p\n", (void *)__kaslr_offset); + pr_cont(" .text @ 0x%p\n", _text); + pr_cont(" .data @ 0x%p\n", _sdata); + pr_cont(" .bss @ 0x%p\n", __bss_start); } } -- cgit v1.2.3