From b4c4c6ee93501a46d58d5511fc8bb9aeb4508c6d Mon Sep 17 00:00:00 2001 From: Jonas Bonn Date: Fri, 6 Apr 2012 12:52:54 +0200 Subject: openrisc: implement irqdomains This moves OpenRISC to using the irqdomain infrastructure. This doesn't fundamentally change anything other than that it will be easier to have multiple interrupt controllers in the future. Signed-off-by: Jonas Bonn --- arch/openrisc/kernel/irq.c | 79 +++++++++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 32 deletions(-) (limited to 'arch/openrisc/kernel') diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c index 4bfead220956..15c5ea3e98d4 100644 --- a/arch/openrisc/kernel/irq.c +++ b/arch/openrisc/kernel/irq.c @@ -24,7 +24,7 @@ #include #include #include - +#include #include /* read interrupt enabled status */ @@ -98,6 +98,7 @@ static void or1k_pic_mask_ack(struct irq_data *data) #endif } +#if 0 static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type) { /* There's nothing to do in the PIC configuration when changing @@ -107,43 +108,64 @@ static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type) return irq_setup_alt_chip(data, flow_type); } +#endif + +static struct irq_chip or1k_dev = { + .name = "or1k-PIC", + .irq_unmask = or1k_pic_unmask, + .irq_mask = or1k_pic_mask, + .irq_ack = or1k_pic_ack, + .irq_mask_ack = or1k_pic_mask_ack, +}; + +static struct irq_domain *root_domain; static inline int pic_get_irq(int first) { - int irq; + int hwirq; - irq = ffs(mfspr(SPR_PICSR) >> first); + hwirq = ffs(mfspr(SPR_PICSR) >> first); + if (!hwirq) + return NO_IRQ; + else + hwirq = hwirq + first -1; - return irq ? irq + first - 1 : NO_IRQ; + return irq_find_mapping(root_domain, hwirq); } -static void __init or1k_irq_init(void) + +static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct irq_chip_generic *gc; - struct irq_chip_type *ct; + irq_set_chip_and_handler_name(irq, &or1k_dev, + handle_level_irq, "level"); + irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE); - /* Disable all interrupts until explicitly requested */ - mtspr(SPR_PICMR, (0UL)); + return 0; +} - gc = irq_alloc_generic_chip("or1k-PIC", 1, 0, 0, handle_level_irq); - ct = gc->chip_types; +static const struct irq_domain_ops or1k_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = or1k_map, +}; - ct->chip.irq_unmask = or1k_pic_unmask; - ct->chip.irq_mask = or1k_pic_mask; - ct->chip.irq_ack = or1k_pic_ack; - ct->chip.irq_mask_ack = or1k_pic_mask_ack; - ct->chip.irq_set_type = or1k_pic_set_type; +/* + * This sets up the IRQ domain for the PIC built in to the OpenRISC + * 1000 CPU. This is the "root" domain as these are the interrupts + * that directly trigger an exception in the CPU. + */ +static void __init or1k_irq_init(void) +{ + struct device_node *intc = NULL; - /* The OR1K PIC can handle both level and edge trigged - * interrupts in roughly the same manner - */ -#if 0 - /* FIXME: chip.type??? */ - ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK; -#endif + /* The interrupt controller device node is mandatory */ + intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic"); + BUG_ON(!intc); - irq_setup_generic_chip(gc, IRQ_MSK(NR_IRQS), 0, - IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); + /* Disable all interrupts until explicitly requested */ + mtspr(SPR_PICMR, (0UL)); + + root_domain = irq_domain_add_linear(intc, 32, + &or1k_irq_domain_ops, NULL); } void __init init_IRQ(void) @@ -164,10 +186,3 @@ void __irq_entry do_IRQ(struct pt_regs *regs) irq_exit(); set_irq_regs(old_regs); } - -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); -- cgit v1.2.3 From ad188f955a79f5501b0cd5bde2b0621b3c78044a Mon Sep 17 00:00:00 2001 From: Jonas Bonn Date: Fri, 6 Apr 2012 13:04:12 +0200 Subject: openrisc: remove unnecessary includes Signed-off-by: Jonas Bonn --- arch/openrisc/kernel/irq.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/openrisc/kernel') diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c index 15c5ea3e98d4..e935b9d8eee1 100644 --- a/arch/openrisc/kernel/irq.c +++ b/arch/openrisc/kernel/irq.c @@ -14,15 +14,11 @@ * 2 of the License, or (at your option) any later version. */ -#include -#include #include #include #include #include #include -#include -#include #include #include #include -- cgit v1.2.3 From 7b903e6c021a5462e26ea7a8f014fa60b6782bdb Mon Sep 17 00:00:00 2001 From: Jonas Bonn Date: Sun, 15 Apr 2012 21:09:25 +0200 Subject: openrisc: provide dma_map_ops This switches OpenRISC over to fully using the generic dma-mapping framework. This was almost already the case as the architecture's implementation was essentially a copy of the generic header. This also brings this architecture in line with the recent changes to dma_map_ops (adding attributes to ops->alloc). Signed-off-by: Jonas Bonn --- arch/openrisc/kernel/dma.c | 109 ++++++++++++++++++++++++++++++--------------- 1 file changed, 73 insertions(+), 36 deletions(-) (limited to 'arch/openrisc/kernel') diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c index f1c8ee2895d0..0b77ddb1ee07 100644 --- a/arch/openrisc/kernel/dma.c +++ b/arch/openrisc/kernel/dma.c @@ -21,13 +21,16 @@ #include #include +#include +#include #include #include #include -static int page_set_nocache(pte_t *pte, unsigned long addr, - unsigned long next, struct mm_walk *walk) +static int +page_set_nocache(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) { unsigned long cl; @@ -46,8 +49,9 @@ static int page_set_nocache(pte_t *pte, unsigned long addr, return 0; } -static int page_clear_nocache(pte_t *pte, unsigned long addr, - unsigned long next, struct mm_walk *walk) +static int +page_clear_nocache(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) { pte_val(*pte) &= ~_PAGE_CI; @@ -67,9 +71,19 @@ static int page_clear_nocache(pte_t *pte, unsigned long addr, * cache-inhibit bit on those pages, and makes sure that the pages are * flushed out of the cache before they are used. * + * If the NON_CONSISTENT attribute is set, then this function just + * returns "normal", cachable memory. + * + * There are additional flags WEAK_ORDERING and WRITE_COMBINE to take + * into consideration here, too. All current known implementations of + * the OR1K support only strongly ordered memory accesses, so that flag + * is being ignored for now; uncached but write-combined memory is a + * missing feature of the OR1K. */ -void *or1k_dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) +static void * +or1k_dma_alloc(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp, + struct dma_attrs *attrs) { unsigned long va; void *page; @@ -87,20 +101,23 @@ void *or1k_dma_alloc_coherent(struct device *dev, size_t size, va = (unsigned long)page; - /* - * We need to iterate through the pages, clearing the dcache for - * them and setting the cache-inhibit bit. - */ - if (walk_page_range(va, va + size, &walk)) { - free_pages_exact(page, size); - return NULL; + if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) { + /* + * We need to iterate through the pages, clearing the dcache for + * them and setting the cache-inhibit bit. + */ + if (walk_page_range(va, va + size, &walk)) { + free_pages_exact(page, size); + return NULL; + } } return (void *)va; } -void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle) +static void +or1k_dma_free(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle, struct dma_attrs *attrs) { unsigned long va = (unsigned long)vaddr; struct mm_walk walk = { @@ -108,16 +125,19 @@ void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr, .mm = &init_mm }; - /* walk_page_range shouldn't be able to fail here */ - WARN_ON(walk_page_range(va, va + size, &walk)); + if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) { + /* walk_page_range shouldn't be able to fail here */ + WARN_ON(walk_page_range(va, va + size, &walk)); + } free_pages_exact(vaddr, size); } -dma_addr_t or1k_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir, - struct dma_attrs *attrs) +static dma_addr_t +or1k_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) { unsigned long cl; dma_addr_t addr = page_to_phys(page) + offset; @@ -147,16 +167,18 @@ dma_addr_t or1k_map_page(struct device *dev, struct page *page, return addr; } -void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) +static void +or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) { /* Nothing special to do here... */ } -int or1k_map_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) +static int +or1k_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) { struct scatterlist *s; int i; @@ -169,9 +191,10 @@ int or1k_map_sg(struct device *dev, struct scatterlist *sg, return nents; } -void or1k_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) +static void +or1k_unmap_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) { struct scatterlist *s; int i; @@ -181,9 +204,10 @@ void or1k_unmap_sg(struct device *dev, struct scatterlist *sg, } } -void or1k_sync_single_for_cpu(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void +or1k_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) { unsigned long cl; dma_addr_t addr = dma_handle; @@ -193,9 +217,10 @@ void or1k_sync_single_for_cpu(struct device *dev, mtspr(SPR_DCBIR, cl); } -void or1k_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) +static void +or1k_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) { unsigned long cl; dma_addr_t addr = dma_handle; @@ -205,6 +230,18 @@ void or1k_sync_single_for_device(struct device *dev, mtspr(SPR_DCBFR, cl); } +struct dma_map_ops or1k_dma_map_ops = { + .alloc = or1k_dma_alloc, + .free = or1k_dma_free, + .map_page = or1k_map_page, + .unmap_page = or1k_unmap_page, + .map_sg = or1k_map_sg, + .unmap_sg = or1k_unmap_sg, + .sync_single_for_cpu = or1k_sync_single_for_cpu, + .sync_single_for_device = or1k_sync_single_for_device, +}; +EXPORT_SYMBOL(or1k_dma_map_ops); + /* Number of entries preallocated for DMA-API debugging */ #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) -- cgit v1.2.3 From 207e715ff17b42e022df107210dc8c736a703eb3 Mon Sep 17 00:00:00 2001 From: Jonas Bonn Date: Wed, 18 Apr 2012 12:23:39 +0200 Subject: openrisc: use scratch regs in atomic syscall MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function sys_or1k_atomic was using call-saved registers without restoring their value before returning. This is a faux pas: either we need to restore their values or use scratch regs; the latter is less code so that's the route this patch takes. Thanks to David Hennerström for doing most of the heavy-lifting in tracking this one down. Reported-by: Davd Hennerström Signed-off-by: Jonas Bonn --- arch/openrisc/kernel/entry.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/openrisc/kernel') diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index 6e61af8682b8..ddfcaa828b0e 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -1117,10 +1117,10 @@ ENTRY(sys_rt_sigreturn) ENTRY(sys_or1k_atomic) /* FIXME: This ignores r3 and always does an XCHG */ DISABLE_INTERRUPTS(r17,r19) - l.lwz r30,0(r4) - l.lwz r28,0(r5) - l.sw 0(r4),r28 - l.sw 0(r5),r30 + l.lwz r29,0(r4) + l.lwz r27,0(r5) + l.sw 0(r4),r27 + l.sw 0(r5),r29 ENABLE_INTERRUPTS(r17) l.jr r9 l.or r11,r0,r0 -- cgit v1.2.3