From 9b3b331d0322b60de1bde20528bf974f62804ffa Mon Sep 17 00:00:00 2001 From: Grant Grundler Date: Fri, 21 Oct 2005 22:55:51 -0400 Subject: [PARISC] Properly specify index field to I/D cache flush ops replace use of "0" with "%r0" since PA 1.1 I/D flush ops only take a general register and not an immediate value for the index field. This just forces the code to always be PA 1.1 "clean". From: Joel Soete Signed-off-by: Grant Grundler Signed-off-by: Kyle McMartin --- arch/parisc/kernel/signal.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/parisc/kernel/signal.c') diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c index befdfe700616..82c24e62ab63 100644 --- a/arch/parisc/kernel/signal.c +++ b/arch/parisc/kernel/signal.c @@ -625,11 +625,14 @@ do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall) put_user(0xe0008200, &usp[3]); put_user(0x34140000, &usp[4]); - /* Stack is 64-byte aligned, and we only - * need to flush 1 cache line */ - asm("fdc 0(%%sr3, %0)\n" + /* Stack is 64-byte aligned, and we only need + * to flush 1 cache line. + * Flushing one cacheline is cheap. + * "sync" on bigger (> 4 way) boxes is not. + */ + asm("fdc %%r0(%%sr3, %0)\n" "sync\n" - "fic 0(%%sr3, %0)\n" + "fic %%r0(%%sr3, %0)\n" "sync\n" : : "r"(regs->gr[30])); -- cgit v1.2.3