From f4151b9ba87901eb3a7bc49f418cc352d4e1927e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 20 Nov 2007 21:19:16 +1100 Subject: [POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese Signed-off-by: Josh Boyer --- arch/ppc/kernel/head_44x.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 75bbc937ed73..ebb5a403829f 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -195,7 +195,7 @@ skpinv: addi r4,r4,1 /* Increment */ li r5,0 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) - li r0,0 /* TLB slot 0 */ + li r0,62 /* TLB slot 62 */ tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ -- cgit v1.2.3