From 3cf6fa1e334a3a4af702f92229690195018b747f Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 19 Apr 2010 17:27:17 +0900 Subject: sh: Enable SH-X3 hardware synonym avoidance handling. This enables support for the hardware synonym avoidance handling on SH-X3 CPUs for the case where dcache aliases are possible. icache handling is retained, but we flip on broadcasting of the block invalidations due to the lack of coherency otherwise on SMP. Signed-off-by: Paul Mundt --- arch/sh/mm/cache.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/sh/mm/cache.c') diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index 0f4095d7ac8b..ba401d137bb9 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -334,6 +334,13 @@ void __init cpu_cache_init(void) extern void __weak sh4_cache_init(void); sh4_cache_init(); + + if ((boot_cpu_data.type == CPU_SH7786) || + (boot_cpu_data.type == CPU_SHX3)) { + extern void __weak shx3_cache_init(void); + + shx3_cache_init(); + } } if (boot_cpu_data.family == CPU_FAMILY_SH5) { -- cgit v1.2.3