From 56b4404ed235e9b9339b379ef80c7d04d23905b3 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Wed, 10 Jul 2019 19:01:21 +0200 Subject: ARM64: dts: colibri-imx8x: Unify formatting of devicetree This patch also puts some comments. Signed-off-by: Philippe Schenker --- .../boot/dts/freescale/fsl-imx8qxp-colibri.dtsi | 440 ++++++++++++--------- 1 file changed, 244 insertions(+), 196 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi index d8dc4fcf2077..e13f3405ba62 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi @@ -94,76 +94,83 @@ pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; colibri-imx8qxp { - pinctrl_ad7879_int: ad7879-int { /* TOUCH Interrupt */ + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { fsl,pins = < - SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x00000021 + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 >; }; + /* Colibri Analogue Inputs */ pinctrl_adc0: adc0grp { fsl,pins = < - SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 - SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 - SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 - SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ >; }; pinctrl_csi_ctl: csictlgrp { fsl,pins = < - SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */ - SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */ + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ >; }; + /* Colibri UART_B */ pinctrl_lpuart0: lpuart0grp { fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 - SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 - SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ >; }; + /* Colibri UART_C */ pinctrl_lpuart2: lpuart2grp { fsl,pins = < - SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 - SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ >; }; + /* Colibri UART_A */ pinctrl_lpuart3: lpuart3grp { fsl,pins = < - SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 - SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ >; }; + /* Colibri UART_A Control */ pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { fsl,pins = < - SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */ - SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */ - SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */ - SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */ - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */ - SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */ + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + SC_P_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ >; }; + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ pinctrl_fec1: fec1grp { fsl,pins = < SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 >; }; @@ -171,346 +178,367 @@ fsl,pins = < SC_P_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000041 - SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x00000041 - SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x00000041 - SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000041 - SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x00000041 - SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x00000041 - SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x00000041 - SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x00000041 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 >; }; + /* Colibri LCD Back-Light GPIO */ pinctrl_gpio_bl_on: gpio-bl-on { fsl,pins = < - SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000060 + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ >; }; pinctrl_hog0: hog0grp { fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ >; }; pinctrl_hog1: hog1grp { fsl,pins = < - SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */ - SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */ - SC_P_CSI_D07_CI_PI_D09 0x00000061 - SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */ - SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */ - SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */ - SC_P_CSI_D02_CI_PI_D04 0x00000061 - SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */ - SC_P_CSI_D06_CI_PI_D08 0x00000061 - SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */ - SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */ - SC_P_CSI_D03_CI_PI_D05 0x00000061 - SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */ - SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */ - SC_P_CSI_D00_CI_PI_D02 0x00000061 - SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */ - SC_P_CSI_D01_CI_PI_D03 0x00000061 - SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */ - SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */ - SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */ - SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */ - SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */ - SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */ - SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */ - SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */ - SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */ - SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */ - SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */ + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x20 /* SODIMM 45 */ + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ + SC_P_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x20 /* SODIMM 73 */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + SC_P_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + SC_P_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + SC_P_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + SC_P_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + SC_P_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ >; }; pinctrl_hog2: hog2grp { fsl,pins = < - SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */ - SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */ + SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ >; }; - /* This pin is used in the SCFW as a UART. Using it from + /* + * This pin is used in the SCFW as a UART. Using it from * Linux would require rewritting the SCFW board file. */ pinctrl_hog_scfw: hogscfwgrp { fsl,pins = < - SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x00000020 /* 144 */ + SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ >; }; /* On Module I2C */ pinctrl_i2c0: i2c0grp { fsl,pins = < - SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 >; }; - /* Off Module I2C */ + /* Colibri I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = < - SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 - SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ >; }; + /* Colibri optional CAN on UART_B RTS/CTS */ pinctrl_flexcan1: flexcan0grp { fsl,pins = < - SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 - SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ >; }; + /* Colibri optional CAN on PS2 */ pinctrl_flexcan2: flexcan1grp { fsl,pins = < - SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 - SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ >; }; + /* On module wifi module */ pinctrl_pcieb: pciebgrp { fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 - SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x00000060 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ >; }; + /* Colibri PWM_A */ pinctrl_pwm_a: pwma { /* both pins are connected together, reserve the unused CSI_D05 */ fsl,pins = < - SC_P_CSI_D05_CI_PI_D07 0x00000061 - SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + SC_P_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ >; }; + /* Colibri PWM_B */ pinctrl_pwm_b: pwmb { fsl,pins = < - SC_P_UART1_TX_LSIO_PWM0_OUT 0x00000060 + SC_P_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ >; }; + /* Colibri PWM_C */ pinctrl_pwm_c: pwmc { fsl,pins = < - SC_P_UART1_RX_LSIO_PWM1_OUT 0x00000060 + SC_P_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ >; }; + /* Colibri PWM_D */ pinctrl_pwm_d: pwmd { /* both pins are connected together, reserve the unused CSI_D04 */ fsl,pins = < - SC_P_CSI_D04_CI_PI_D06 0x00000061 - SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x00000060 + SC_P_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ >; }; + /* On-module I2S */ pinctrl_sai0: sai0grp { fsl,pins = < - SC_P_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - SC_P_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - SC_P_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - SC_P_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + SC_P_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + SC_P_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + SC_P_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + SC_P_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 >; }; + /* Colibri Audio Analogue Microphone GND */ pinctrl_sgtl5000: sgtl5000 { fsl,pins = < /* MIC GND EN */ - SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x00000041 + SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 >; }; + /* On-module SGTL5000 clock */ pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { fsl,pins = < - SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x00000021 + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 >; }; - /*INT*/ + /* On-module USB interrupt */ pinctrl_usb3503a: usb3503a-grp { fsl,pins = < - SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061 + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 >; }; + /* Colibri USB Client Cable Detect */ pinctrl_usbc_det: usbc-det { fsl,pins = < - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ >; }; pinctrl_ext_io0: ext-io0 { fsl,pins = < - SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ >; }; + /* Colibri Parallel RGB LCD Interface */ pinctrl_lcdif: lcdif-pins { fsl,pins = < - SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 - SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 - SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 - SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 - SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000060 - - SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 - SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000060 - SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 - SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 - SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 - SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 - SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 - SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 - SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 - SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 - SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 - SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 - SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 - SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 - SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 - SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 - SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 - SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x00000060 - SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000060 - SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ >; }; + /* USB Host Power Enable */ pinctrl_usbh1_reg: usbh1-reg { fsl,pins = < - SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ >; }; + /* On-module eMMC */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 >; }; + /* Colibri SDCard CardDetect */ pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < - SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ >; }; + /* Colibri SDCard */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 >; }; + /* MIPI DSI0 I2C on FFC (X2) */ pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { fsl,pins = < - SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 - SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ >; }; + /* On-module MIPI CSI I2C accessible via FFC (X3) */ pinctrl_i2c0_mipi_csi: mipi_csi_i2c0_grp { fsl,pins = < - SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 - SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ >; }; + /* Colibri SPI */ pinctrl_lpspi2: lpspi2 { fsl,pins = < - SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021 - SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 - SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 - SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ >; }; pinctrl_wifi: wifigrp { fsl,pins = < - SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x00000020 + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 >; }; }; }; +/* Colibri Analogue Inputs */ &adc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc0>; @@ -518,7 +546,7 @@ status = "okay"; }; -/* CAN on UART_B RTS/CTS */ +/* Colibri optional CAN on UART_B RTS/CTS */ &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; @@ -526,6 +554,7 @@ status = "disabled"; }; +/* Colibri optional CAN on PS2 */ &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -533,12 +562,14 @@ status = "okay"; }; +/* Colibri UART_B */ &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; +/* Colibri UART_C */ &lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; @@ -549,6 +580,7 @@ debug_console; }; +/* Colibri UART_A */ &lpuart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; @@ -648,6 +680,7 @@ status = "okay"; }; +/* Colibri Ethernet */ &fec1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; @@ -674,6 +707,7 @@ }; }; +/* On-module I2C */ &i2c0 { #address-cells = <1>; #size-cells = <0>; @@ -682,8 +716,10 @@ pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; status = "okay"; - /* IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000 - So do the pinmuxing and setup for both here */ + /* + * IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000 + * So do the pinmuxing and setup for both here + */ assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, @@ -749,6 +785,7 @@ }; }; +/* Colibri I2C */ &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -764,6 +801,7 @@ }; }; +/* On-module MIPI CSI I2C accessible via FFC (X3) */ &i2c0_mipi_lvds1 { #address-cells = <1>; #size-cells = <0>; @@ -811,6 +849,7 @@ status = "okay"; }; +/* Colibri SPI */ &lpspi2 { #address-cells = <1>; #size-cells = <0>; @@ -827,6 +866,7 @@ }; }; +/* On-module MIPI CSI accessible via FFC (X3) */ &mipi_csi_0 { #address-cells = <1>; #size-cells = <0>; @@ -844,6 +884,7 @@ }; }; +/* On-module PCIe for wifi */ &pcieb{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; @@ -857,24 +898,28 @@ status = "okay"; }; +/* Colibri PWM_A */ &pwm_adma_lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_a>; status = "okay"; }; +/* Colibri PWM_B */ &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_b>; status = "okay"; }; +/* Colibri PWM_C */ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_c>; status = "okay"; }; +/* Colibri PWM_D */ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_d>; @@ -890,6 +935,7 @@ status = "okay"; }; +/* On-module I2S */ &sai0 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -931,6 +977,7 @@ }; }; +/* On-module eMMC */ &usdhc1 { bus-width = <8>; non-removable; @@ -941,6 +988,7 @@ status = "okay"; }; +/* Colibri SDCard */ &usdhc2 { bus-width = <4>; cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; -- cgit v1.2.3