From 65e8a5257dc71b5c2612b97ad94b910bab60a242 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 17 May 2013 18:24:19 -0700 Subject: ARM: tegra11: dvfs: Update CPU dvfs tables Bug 1291764 Change-Id: I92c652e9ecbec366c017ab2eda0e51b1dd42cb17 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/230033 (cherry picked from commit 8c42909312f5082d3e62f0fbc7b0556e7aed099d) Reviewed-on: http://git-master/r/242587 GVS: Gerrit_Virtual_Submit Reviewed-by: Sang-Hun Lee Tested-by: Sang-Hun Lee Reviewed-by: Matt Wagner --- arch/arm/mach-tegra/tegra11_dvfs.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra11_dvfs.c b/arch/arm/mach-tegra/tegra11_dvfs.c index c8bfcb440aca..072a9ade160f 100644 --- a/arch/arm/mach-tegra/tegra11_dvfs.c +++ b/arch/arm/mach-tegra/tegra11_dvfs.c @@ -145,11 +145,11 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .cvb_table = { /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 900000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 940000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 940000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 990000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 990000, 0, 0} }, + { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, + { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, + { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, + { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, + { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, @@ -181,11 +181,11 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .cvb_table = { /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 900000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 940000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 940000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 990000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 990000, 0, 0} }, + { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, + { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, + { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, + { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, + { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, @@ -217,11 +217,11 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .cvb_table = { /*f dfll: c0, c1, c2 pll: c0, c1, c2 */ { 306000, { 2190643, -141851, 3576}, { 900000, 0, 0} }, - { 408000, { 2250968, -144331, 3576}, { 900000, 0, 0} }, - { 510000, { 2313333, -146811, 3576}, { 940000, 0, 0} }, - { 612000, { 2377738, -149291, 3576}, { 940000, 0, 0} }, - { 714000, { 2444183, -151771, 3576}, { 990000, 0, 0} }, - { 816000, { 2512669, -154251, 3576}, { 990000, 0, 0} }, + { 408000, { 2250968, -144331, 3576}, { 950000, 0, 0} }, + { 510000, { 2313333, -146811, 3576}, { 970000, 0, 0} }, + { 612000, { 2377738, -149291, 3576}, { 1000000, 0, 0} }, + { 714000, { 2444183, -151771, 3576}, { 1020000, 0, 0} }, + { 816000, { 2512669, -154251, 3576}, { 1020000, 0, 0} }, { 918000, { 2583194, -156731, 3576}, { 1030000, 0, 0} }, {1020000, { 2655759, -159211, 3576}, { 1030000, 0, 0} }, {1122000, { 2730365, -161691, 3576}, { 1090000, 0, 0} }, @@ -272,9 +272,9 @@ static struct dvfs core_dvfs_table[] = { #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM CORE_DVFS("emc", -1, -1, 1, KHZ, 1, 1, 1, 1, 800000, 800000, 933000, 933000, 1066000), - CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 228000, 306000, 396000, 528000, 648000, 696000, 696000, 696000, 696000), - CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 324000, 432000, 528000, 612000, 696000, 696000, 696000, 696000, 696000), - CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 324000, 432000, 528000, 612000, 792000, 816000, 816000, 816000, 816000), + CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 228000, 306000, 396000, 510000, 648000, 696000, 696000, 696000, 696000), + CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 324000, 396000, 510000, 612000, 696000, 696000, 696000, 696000, 696000), + CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 324000, 396000, 510000, 612000, 768000, 816000, 816000, 816000, 816000), CORE_DVFS("sbus", 0, 0, 1, KHZ, 132000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000), CORE_DVFS("sbus", 0, 1, 1, KHZ, 180000, 228000, 300000, 336000, 336000, 336000, 336000, 336000, 336000), -- cgit v1.2.3