From ab7fcb00afc6e6d23040e9f53932f38d34048f9b Mon Sep 17 00:00:00 2001
From: Gary King <gking@nvidia.com>
Date: Wed, 10 Feb 2010 19:00:48 -0800
Subject: tegra board: update cache init to support PL3XO & L2XO configs

prepare the tegra initialization routine for an upcoming change to
the L2 cache code which will move from using CONFIG_CACHE_L2X0 to
CONFIG_CACHE_PL3X0 in order to improve performance

Change-Id: Icd2b6836682e5f76427b63f9b7785318e9547c07
---
 arch/arm/mach-tegra/init_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/mach-tegra/init_common.c b/arch/arm/mach-tegra/init_common.c
index b054a1bf40af..19bb822acb23 100755
--- a/arch/arm/mach-tegra/init_common.c
+++ b/arch/arm/mach-tegra/init_common.c
@@ -787,7 +787,7 @@ fail:
 }
 #endif
 
-#if !defined(CONFIG_CACHE_L2X0)
+#if !(defined(CONFIG_CACHE_PL3X0) || defined(CONFIG_CACHE_L2X0))
 #define tegra_pl310_init() do {} while (0)
 #else
 #include <asm/hardware/cache-l2x0.h>
-- 
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