From c8990b1f0ab269292f25343191e79f86bff93c96 Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Wed, 29 Jun 2011 10:52:53 +0530 Subject: ARM: tegra: clock: Update bus operations Relaxed bus set rate success condition: instead of exact rate require closest rate below the request (makes bus clocks configurable from sources/PLLs with variable frequencies). Bug 821534 Change-Id: I491f8841cf2ca206a54beb1c24c84f470d08eb4b Reviewed-on: http://git-master/r/38868 Reviewed-by: Manish Tuteja Tested-by: Manish Tuteja --- arch/arm/mach-tegra/tegra2_clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 39987f4dd0c2..bf92cee1aa3e 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -540,7 +540,7 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) unsigned long parent_rate = clk_get_rate(c->parent); int i; for (i = 1; i <= 4; i++) { - if (rate == parent_rate / i) { + if (rate >= parent_rate / i) { val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); val |= (i - 1) << c->reg_shift; clk_writel(val, c->reg); -- cgit v1.2.3