From 0bf0ff82c34da02ee5795101b328225a2d519594 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 23 Feb 2015 13:30:28 -0800 Subject: clk: qcom: Fix i2c frequency table PXO is 25MHz, not 27MHz. Fix the table. Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd Reviewed-by: Andy Gross Tested-by: Andy Gross Signed-off-by: Michael Turquette --- drivers/clk/qcom/gcc-ipq806x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom/gcc-ipq806x.c') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index cbdc31dea7f4..a015bb06c09b 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -525,8 +525,8 @@ static struct freq_tbl clk_tbl_gsbi_qup[] = { { 10800000, P_PXO, 1, 2, 5 }, { 15060000, P_PLL8, 1, 2, 51 }, { 24000000, P_PLL8, 4, 1, 4 }, + { 25000000, P_PXO, 1, 0, 0 }, { 25600000, P_PLL8, 1, 1, 15 }, - { 27000000, P_PXO, 1, 0, 0 }, { 48000000, P_PLL8, 4, 1, 2 }, { 51200000, P_PLL8, 1, 2, 15 }, { } -- cgit v1.2.3 From 293d2e97b37f545bb36aef78cd549d9e6cd66e7f Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Fri, 20 Mar 2015 18:30:26 +0200 Subject: clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq806x.c | 46 ++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 22 deletions(-) (limited to 'drivers/clk/qcom/gcc-ipq806x.c') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a015bb06c09b..ee73cc7f6e55 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -140,15 +140,17 @@ static struct clk_regmap pll14_vote = { }, }; -#define P_PXO 0 -#define P_PLL8 1 -#define P_PLL3 1 -#define P_PLL0 2 -#define P_CXO 2 +enum { + P_PXO, + P_PLL8, + P_PLL3, + P_PLL0, + P_CXO, +}; -static const u8 gcc_pxo_pll8_map[] = { - [P_PXO] = 0, - [P_PLL8] = 3, +static const struct parent_map gcc_pxo_pll8_map[] = { + { P_PXO, 0 }, + { P_PLL8, 3 } }; static const char *gcc_pxo_pll8[] = { @@ -156,10 +158,10 @@ static const char *gcc_pxo_pll8[] = { "pll8_vote", }; -static const u8 gcc_pxo_pll8_cxo_map[] = { - [P_PXO] = 0, - [P_PLL8] = 3, - [P_CXO] = 5, +static const struct parent_map gcc_pxo_pll8_cxo_map[] = { + { P_PXO, 0 }, + { P_PLL8, 3 }, + { P_CXO, 5 } }; static const char *gcc_pxo_pll8_cxo[] = { @@ -168,14 +170,14 @@ static const char *gcc_pxo_pll8_cxo[] = { "cxo", }; -static const u8 gcc_pxo_pll3_map[] = { - [P_PXO] = 0, - [P_PLL3] = 1, +static const struct parent_map gcc_pxo_pll3_map[] = { + { P_PXO, 0 }, + { P_PLL3, 1 } }; -static const u8 gcc_pxo_pll3_sata_map[] = { - [P_PXO] = 0, - [P_PLL3] = 6, +static const struct parent_map gcc_pxo_pll3_sata_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 } }; static const char *gcc_pxo_pll3[] = { @@ -183,10 +185,10 @@ static const char *gcc_pxo_pll3[] = { "pll3", }; -static const u8 gcc_pxo_pll8_pll0[] = { - [P_PXO] = 0, - [P_PLL8] = 3, - [P_PLL0] = 2, +static const struct parent_map gcc_pxo_pll8_pll0[] = { + { P_PXO, 0 }, + { P_PLL8, 3 }, + { P_PLL0, 2 } }; static const char *gcc_pxo_pll8_pll0_map[] = { -- cgit v1.2.3 From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 2 Apr 2015 11:20:41 +0530 Subject: clk: qcom: Add EBI2 clocks for IPQ806x The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/clk/qcom/gcc-ipq806x.c') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index ee73cc7f6e55..a50936a17376 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -2172,6 +2172,36 @@ static struct clk_branch usb_fs1_h_clk = { }, }; +static struct clk_branch ebi2_clk = { + .hwcg_reg = 0x3b00, + .hwcg_bit = 6, + .halt_reg = 0x2fcc, + .halt_bit = 1, + .clkr = { + .enable_reg = 0x3b00, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ebi2_clk", + .ops = &clk_branch_ops, + .flags = CLK_IS_ROOT, + }, + }, +}; + +static struct clk_branch ebi2_aon_clk = { + .halt_reg = 0x2fcc, + .halt_bit = 0, + .clkr = { + .enable_reg = 0x3b00, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "ebi2_always_on_clk", + .ops = &clk_branch_ops, + .flags = CLK_IS_ROOT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2275,6 +2305,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, + [EBI2_CLK] = &ebi2_clk.clkr, + [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -- cgit v1.2.3