From f7a9ee81a88b83915e7c15895c507abede44b0c5 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 29 Mar 2018 09:09:39 -0400 Subject: drm/amdgpu: Add support for SRBM selection v3 Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f44a83ab2bf4..0193f6ced00b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -890,6 +890,7 @@ struct amdgpu_gfx_funcs { void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); + void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue); }; struct amdgpu_ngg_buf { @@ -1812,6 +1813,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) +#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) /* Common functions */ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, -- cgit v1.2.3 From 1b59fb036a3e2a5bc4ce3d02c3fb473e595400c9 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 10 Apr 2018 12:30:59 +0800 Subject: drm/amdgpu: add MP1 and THM hw ip base reg offset Signed-off-by: Evan Quan Reviewed-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0193f6ced00b..c8b605f3dc05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1379,6 +1379,7 @@ enum amd_hw_ip_block_type { ATHUB_HWIP, NBIO_HWIP, MP0_HWIP, + MP1_HWIP, UVD_HWIP, VCN_HWIP = UVD_HWIP, VCE_HWIP, @@ -1388,6 +1389,7 @@ enum amd_hw_ip_block_type { SMUIO_HWIP, PWR_HWIP, NBIF_HWIP, + THM_HWIP, MAX_HWIP }; -- cgit v1.2.3