From 1eb22bd38ac58a1be6e7e0ae6dd4ab6d604a27d6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 Nov 2015 10:34:45 -0500 Subject: drm/amdgpu: add read_bios_from_rom callback for CI parts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Read the vbios image directly from the rom. Reviewed-by: Jammy Zhou Reviewed-by: Christian König Reviewed-by: Monk Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c') diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 484710cfdf82..61689f094ba8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -929,6 +929,37 @@ static bool cik_read_disabled_bios(struct amdgpu_device *adev) return r; } +static bool cik_read_bios_from_rom(struct amdgpu_device *adev, + u8 *bios, u32 length_bytes) +{ + u32 *dw_ptr; + unsigned long flags; + u32 i, length_dw; + + if (bios == NULL) + return false; + if (length_bytes == 0) + return false; + /* APU vbios image is part of sbios image */ + if (adev->flags & AMD_IS_APU) + return false; + + dw_ptr = (u32 *)bios; + length_dw = ALIGN(length_bytes, 4) / 4; + /* take the smc lock since we are using the smc index */ + spin_lock_irqsave(&adev->smc_idx_lock, flags); + /* set rom index to 0 */ + WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); + WREG32(mmSMC_IND_DATA_0, 0); + /* set index to data for continous read */ + WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); + for (i = 0; i < length_dw; i++) + dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return true; +} + static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { {mmGRBM_STATUS, false}, {mmGB_ADDR_CONFIG, false}, @@ -2267,6 +2298,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) static const struct amdgpu_asic_funcs cik_asic_funcs = { .read_disabled_bios = &cik_read_disabled_bios, + .read_bios_from_rom = &cik_read_bios_from_rom, .read_register = &cik_read_register, .reset = &cik_asic_reset, .set_vga_state = &cik_vga_set_state, -- cgit v1.2.3 From 1f7371b2a5faf139465f0af386cccbb54b832534 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 2 Dec 2015 17:46:21 -0500 Subject: drm/amd/powerplay: add basic powerplay framework amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu Signed-off-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c') diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 61689f094ba8..c7c298b88170 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -65,6 +65,7 @@ #include "oss/oss_2_0_sh_mask.h" #include "amdgpu_amdkfd.h" +#include "amdgpu_powerplay.h" /* * Indirect registers accessor @@ -1953,7 +1954,7 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = .major = 7, .minor = 0, .rev = 0, - .funcs = &ci_dpm_ip_funcs, + .funcs = &amdgpu_pp_ip_funcs, }, { .type = AMD_IP_BLOCK_TYPE_DCE, @@ -2021,7 +2022,7 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = .major = 7, .minor = 0, .rev = 0, - .funcs = &ci_dpm_ip_funcs, + .funcs = &amdgpu_pp_ip_funcs, }, { .type = AMD_IP_BLOCK_TYPE_DCE, @@ -2089,7 +2090,7 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] = .major = 7, .minor = 0, .rev = 0, - .funcs = &kv_dpm_ip_funcs, + .funcs = &amdgpu_pp_ip_funcs, }, { .type = AMD_IP_BLOCK_TYPE_DCE, @@ -2157,7 +2158,7 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] = .major = 7, .minor = 0, .rev = 0, - .funcs = &kv_dpm_ip_funcs, + .funcs = &amdgpu_pp_ip_funcs, }, { .type = AMD_IP_BLOCK_TYPE_DCE, @@ -2225,7 +2226,7 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = .major = 7, .minor = 0, .rev = 0, - .funcs = &kv_dpm_ip_funcs, + .funcs = &amdgpu_pp_ip_funcs, }, { .type = AMD_IP_BLOCK_TYPE_DCE, -- cgit v1.2.3 From d0dd7f0cc345fc8757148004639e1993ba183bd6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 11 Nov 2015 19:45:06 -0500 Subject: drm/amdgpu: store pcie gen mask and link width We'll need this later for pcie dpm. Reviewed-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c') diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index c7c298b88170..fd9c9588ef46 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -32,6 +32,7 @@ #include "amdgpu_vce.h" #include "cikd.h" #include "atom.h" +#include "amd_pcie.h" #include "cik.h" #include "gmc_v7_0.h" @@ -1595,8 +1596,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) { struct pci_dev *root = adev->pdev->bus->self; int bridge_pos, gpu_pos; - u32 speed_cntl, mask, current_data_rate; - int ret, i; + u32 speed_cntl, current_data_rate; + int i; u16 tmp16; if (pci_is_root_bus(adev->pdev->bus)) @@ -1608,23 +1609,20 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) if (adev->flags & AMD_IS_APU) return; - ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); - if (ret != 0) - return; - - if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) + if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) return; speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; - if (mask & DRM_PCIE_SPEED_80) { + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { if (current_data_rate == 2) { DRM_INFO("PCIE gen 3 link speeds already enabled\n"); return; } DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); - } else if (mask & DRM_PCIE_SPEED_50) { + } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { if (current_data_rate == 1) { DRM_INFO("PCIE gen 2 link speeds already enabled\n"); return; @@ -1640,7 +1638,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) if (!gpu_pos) return; - if (mask & DRM_PCIE_SPEED_80) { + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { /* re-try equalization if gen3 is not already enabled */ if (current_data_rate != 2) { u16 bridge_cfg, gpu_cfg; @@ -1735,9 +1733,9 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~0xf; - if (mask & DRM_PCIE_SPEED_80) + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) tmp16 |= 3; /* gen3 */ - else if (mask & DRM_PCIE_SPEED_50) + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) tmp16 |= 2; /* gen2 */ else tmp16 |= 1; /* gen1 */ @@ -2450,6 +2448,8 @@ static int cik_common_early_init(void *handle) return -EINVAL; } + amdgpu_get_pcie_info(adev); + return 0; } -- cgit v1.2.3