From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 424 +++++++++++++++++++++++++++ 1 file changed, 424 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dm_services.h (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h new file mode 100644 index 000000000000..7a3f10354830 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -0,0 +1,424 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * This file defines external dependencies of Display Core. + */ + +#ifndef __DM_SERVICES_H__ + +#define __DM_SERVICES_H__ + +/* TODO: remove when DC is complete. */ +#include "dm_services_types.h" +#include "logger_interface.h" +#include "link_service_types.h" + +#undef DEPRECATED + +/* + * + * general debug capabilities + * + */ +#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER) + +#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) +#define ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + kgdb_breakpoint(); \ + } \ +} while (0) +#else +#define ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + ; \ + } \ +} while (0) +#endif + +#if defined(CONFIG_DEBUG_KERNEL_DC) +#define ASSERT(expr) ASSERT_CRITICAL(expr) + +#else +#define ASSERT(expr) WARN_ON(!(expr)) +#endif + +#define BREAK_TO_DEBUGGER() ASSERT(0) + +#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */ + +#define DC_ERR(...) do { \ + dm_error(__VA_ARGS__); \ + BREAK_TO_DEBUGGER(); \ +} while (0) + +#define dm_alloc(size) kzalloc(size, GFP_KERNEL) +#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) +#define dm_free(ptr) kfree(ptr) + +irq_handler_idx dm_register_interrupt( + struct dc_context *ctx, + struct dc_interrupt_params *int_params, + interrupt_handler ih, + void *handler_args); + + +/* + * + * GPU registers access + * + */ + +#define dm_read_reg(ctx, address) \ + dm_read_reg_func(ctx, address, __func__) + +static inline uint32_t dm_read_reg_func( + const struct dc_context *ctx, + uint32_t address, + const char *func_name) +{ + uint32_t value; + + if (address == 0) { + DC_ERR("invalid register read. address = 0"); + return 0; + } + + value = cgs_read_register(ctx->cgs_device, address); + +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s DC_READ_REG: 0x%x 0x%x\n", func_name, address, value); + } +#endif + return value; +} + +#define dm_write_reg(ctx, address, value) \ + dm_write_reg_func(ctx, address, value, __func__) + +static inline void dm_write_reg_func( + const struct dc_context *ctx, + uint32_t address, + uint32_t value, + const char *func_name) +{ +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s DC_WRITE_REG: 0x%x 0x%x\n", func_name, address, value); + } +#endif + + if (address == 0) { + DC_ERR("invalid register write. address = 0"); + return; + } + cgs_write_register(ctx->cgs_device, address, value); +} + +static inline uint32_t dm_read_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index) +{ + return cgs_read_ind_register(ctx->cgs_device, addr_space, index); +} + +static inline void dm_write_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index, + uint32_t value) +{ + cgs_write_ind_register(ctx->cgs_device, addr_space, index, value); +} + +static inline uint32_t get_reg_field_value_ex( + uint32_t reg_value, + uint32_t mask, + uint8_t shift) +{ + return (mask & reg_value) >> shift; +} + +#define get_reg_field_value(reg_value, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +static inline uint32_t set_reg_field_value_ex( + uint32_t reg_value, + uint32_t value, + uint32_t mask, + uint8_t shift) +{ + return (reg_value & ~mask) | (mask & (value << shift)); +} + +#define set_reg_field_value(reg_value, value, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +uint32_t generic_reg_update_ex(const struct dc_context *ctx, + uint32_t addr, uint32_t reg_val, int n, + uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); + +#define FD(reg_field) reg_field ## __SHIFT, \ + reg_field ## _MASK + +/* + * return number of poll before condition is met + * return 0 if condition is not meet after specified time out tries + */ +unsigned int generic_reg_wait(const struct dc_context *ctx, + uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, + unsigned int delay_between_poll_us, unsigned int time_out_num_tries, + const char *func_name); + +/************************************** + * Power Play (PP) interfaces + **************************************/ + +/* DAL calls this function to notify PP about clocks it needs for the Mode Set. + * This is done *before* it changes DCE clock. + * + * If required clock is higher than current, then PP will increase the voltage. + * + * If required clock is lower than current, then PP will defer reduction of + * voltage until the call to dc_service_pp_post_dce_clock_change(). + * + * \input - Contains clocks needed for Mode Set. + * + * \output - Contains clocks adjusted by PP which DAL should use for Mode Set. + * Valid only if function returns zero. + * + * \returns true - call is successful + * false - call failed + */ +bool dm_pp_pre_dce_clock_change( + struct dc_context *ctx, + struct dm_pp_gpu_clock_range *requested_state, + struct dm_pp_gpu_clock_range *actual_state); + +/* The returned clocks range are 'static' system clocks which will be used for + * mode validation purposes. + * + * \returns true - call is successful + * false - call failed + */ +bool dc_service_get_system_clocks_range( + const struct dc_context *ctx, + struct dm_pp_gpu_clock_range *sys_clks); + +/* Gets valid clocks levels from pplib + * + * input: clk_type - display clk / sclk / mem clk + * + * output: array of valid clock levels for given type in ascending order, + * with invalid levels filtered out + * + */ +bool dm_pp_get_clock_levels_by_type( + const struct dc_context *ctx, + enum dm_pp_clock_type clk_type, + struct dm_pp_clock_levels *clk_level_info); + +bool dm_pp_get_clock_levels_by_type_with_latency( + const struct dc_context *ctx, + enum dm_pp_clock_type clk_type, + struct dm_pp_clock_levels_with_latency *clk_level_info); + +bool dm_pp_get_clock_levels_by_type_with_voltage( + const struct dc_context *ctx, + enum dm_pp_clock_type clk_type, + struct dm_pp_clock_levels_with_voltage *clk_level_info); + +bool dm_pp_notify_wm_clock_changes( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); + +/* DAL calls this function to notify PP about completion of Mode Set. + * For PP it means that current DCE clocks are those which were returned + * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. + * + * If the clocks are higher than before, then PP does nothing. + * + * If the clocks are lower than before, then PP reduces the voltage. + * + * \returns true - call is successful + * false - call failed + */ +bool dm_pp_apply_display_requirements( + const struct dc_context *ctx, + const struct dm_pp_display_configuration *pp_display_cfg); + +bool dm_pp_apply_power_level_change_request( + const struct dc_context *ctx, + struct dm_pp_power_level_change_request *level_change_req); + +bool dm_pp_apply_clock_for_voltage_request( + const struct dc_context *ctx, + struct dm_pp_clock_for_voltage_req *clock_for_voltage_req); + +bool dm_pp_get_static_clocks( + const struct dc_context *ctx, + struct dm_pp_static_clock_info *static_clk_info); + +/****** end of PP interfaces ******/ + +enum platform_method { + PM_GET_AVAILABLE_METHODS = 1 << 0, + PM_GET_LID_STATE = 1 << 1, + PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2 +}; + +struct platform_info_params { + enum platform_method method; + void *data; +}; + +struct platform_info_brightness_caps { + uint8_t ac_level_percentage; + uint8_t dc_level_percentage; +}; + +struct platform_info_ext_brightness_caps { + struct platform_info_brightness_caps basic_caps; + struct data_point { + uint8_t luminance; + uint8_t signal_level; + } data_points[99]; + + uint8_t data_points_num; + uint8_t min_input_signal; + uint8_t max_input_signal; +}; + +bool dm_get_platform_info( + struct dc_context *ctx, + struct platform_info_params *params); + +struct persistent_data_flag { + bool save_per_link; + bool save_per_edid; +}; + +/* Call to write data in registry editor for persistent data storage. + * + * \inputs sink - identify edid/link for registry folder creation + * module name - identify folders for registry + * key name - identify keys within folders for registry + * params - value to write in defined folder/key + * size - size of the input params + * flag - determine whether to save by link or edid + * + * \returns true - call is successful + * false - call failed + * + * sink module key + * ----------------------------------------------------------------------------- + * NULL NULL NULL - failure + * NULL NULL - - create key with param value + * under base folder + * NULL - NULL - create module folder under base folder + * - NULL NULL - failure + * NULL - - - create key under module folder + * with no edid/link identification + * - NULL - - create key with param value + * under base folder + * - - NULL - create module folder under base folder + * - - - - create key under module folder + * with edid/link identification + */ +bool dm_write_persistent_data(struct dc_context *ctx, + const struct dc_sink *sink, + const char *module_name, + const char *key_name, + void *params, + unsigned int size, + struct persistent_data_flag *flag); + + +/* Call to read data in registry editor for persistent data storage. + * + * \inputs sink - identify edid/link for registry folder creation + * module name - identify folders for registry + * key name - identify keys within folders for registry + * size - size of the output params + * flag - determine whether it was save by link or edid + * + * \returns params - value read from defined folder/key + * true - call is successful + * false - call failed + * + * sink module key + * ----------------------------------------------------------------------------- + * NULL NULL NULL - failure + * NULL NULL - - read key under base folder + * NULL - NULL - failure + * - NULL NULL - failure + * NULL - - - read key under module folder + * with no edid/link identification + * - NULL - - read key under base folder + * - - NULL - failure + * - - - - read key under module folder + * with edid/link identification + */ +bool dm_read_persistent_data(struct dc_context *ctx, + const struct dc_sink *sink, + const char *module_name, + const char *key_name, + void *params, + unsigned int size, + struct persistent_data_flag *flag); + +void dm_delay_in_microseconds + (struct dc_context *ctx, unsigned int microSeconds); + +bool dm_query_extended_brightness_caps + (struct dc_context *ctx, enum dm_acpi_display_type display, + struct dm_acpi_atif_backlight_caps *pCaps); + +bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); + +/* + * + * print-out services + * + */ +#define dm_log_to_buffer(buffer, size, fmt, args)\ + vsnprintf(buffer, size, fmt, args) + +long dm_get_pid(void); +long dm_get_tgid(void); + +#endif /* __DM_SERVICES_H__ */ -- cgit v1.2.3 From 2a0998846d2eadabf8c5770f66feb3cb04ad88b5 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 13 Dec 2016 16:41:07 +1000 Subject: drm/amd/display: drop register logger and pid/tgid getters While I'm sure this is useful I think we should bring it back later. It's usage of pid/tgid is incorrect, you have to get/put pid/tgids not store them away. Signed-off-by: Dave Airlie Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 7a3f10354830..f3f9a401160c 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -109,12 +109,6 @@ static inline uint32_t dm_read_reg_func( value = cgs_read_register(ctx->cgs_device, address); -#if defined(__DAL_REGISTER_LOGGER__) - if (true == dal_reg_logger_should_dump_register()) { - dal_reg_logger_rw_count_increment(); - DRM_INFO("%s DC_READ_REG: 0x%x 0x%x\n", func_name, address, value); - } -#endif return value; } @@ -127,13 +121,6 @@ static inline void dm_write_reg_func( uint32_t value, const char *func_name) { -#if defined(__DAL_REGISTER_LOGGER__) - if (true == dal_reg_logger_should_dump_register()) { - dal_reg_logger_rw_count_increment(); - DRM_INFO("%s DC_WRITE_REG: 0x%x 0x%x\n", func_name, address, value); - } -#endif - if (address == 0) { DC_ERR("invalid register write. address = 0"); return; @@ -418,7 +405,4 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) -long dm_get_pid(void); -long dm_get_tgid(void); - #endif /* __DM_SERVICES_H__ */ -- cgit v1.2.3 From e285917063641f00086242d6c927ace9de24c357 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 13 Dec 2016 16:41:08 +1000 Subject: drm/amd/display: drop get platform info Signed-off-by: Dave Airlie Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 32 ---------------------------- 1 file changed, 32 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index f3f9a401160c..11a0abfd3418 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -282,38 +282,6 @@ bool dm_pp_get_static_clocks( /****** end of PP interfaces ******/ -enum platform_method { - PM_GET_AVAILABLE_METHODS = 1 << 0, - PM_GET_LID_STATE = 1 << 1, - PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2 -}; - -struct platform_info_params { - enum platform_method method; - void *data; -}; - -struct platform_info_brightness_caps { - uint8_t ac_level_percentage; - uint8_t dc_level_percentage; -}; - -struct platform_info_ext_brightness_caps { - struct platform_info_brightness_caps basic_caps; - struct data_point { - uint8_t luminance; - uint8_t signal_level; - } data_points[99]; - - uint8_t data_points_num; - uint8_t min_input_signal; - uint8_t max_input_signal; -}; - -bool dm_get_platform_info( - struct dc_context *ctx, - struct platform_info_params *params); - struct persistent_data_flag { bool save_per_link; bool save_per_edid; -- cgit v1.2.3 From bf72726358adfedcf1c268690521891809332151 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sat, 14 Jan 2017 01:44:52 -0500 Subject: drm/amd/display: assert if mask is 0 in set_reg_field_value_ex - mask = 0 means something is wrong in caller and no register field will be updated Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 11a0abfd3418..052a43af1bd3 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -165,6 +165,7 @@ static inline uint32_t set_reg_field_value_ex( uint32_t mask, uint8_t shift) { + ASSERT(mask != 0); return (reg_value & ~mask) | (mask & (value << shift)); } -- cgit v1.2.3 From 871ffb606a3eb9b29891b25228f569899bbd216c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 6 Feb 2017 15:07:19 -0500 Subject: drm/amd/display: fix psr status wait Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eagle Yeh Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 052a43af1bd3..73c0f1f83999 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -103,7 +103,7 @@ static inline uint32_t dm_read_reg_func( uint32_t value; if (address == 0) { - DC_ERR("invalid register read. address = 0"); + DC_ERR("invalid register read; address = 0\n"); return 0; } -- cgit v1.2.3 From 2c8ad2d5a20c8b7425b547dd4a969ffecad29b39 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:20:24 -0400 Subject: drm/amd/display: Enable DCE12 support This wires DCE12 support into DC and enables it. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 73c0f1f83999..bdc7cb045eed 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,6 +192,89 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + +/* These macros need to be used with soc15 registers in order to retrieve + * the actual offset. + */ +#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) +#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) + +#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ + dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) + +#define dm_read_reg_soc15(ctx, reg, inst_offset) \ + dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) + +#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ + dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \ + n, __VA_ARGS__) + +#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ + n, __VA_ARGS__) + +#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +/* TODO get rid of this pos*/ +static inline bool wait_reg_func( + const struct dc_context *ctx, + uint32_t addr, + uint32_t mask, + uint8_t shift, + uint32_t condition_value, + unsigned int interval_us, + unsigned int timeout_us) +{ + uint32_t field_value; + uint32_t reg_val; + unsigned int count = 0; + + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) + timeout_us *= 655; /* 6553 give about 30 second before time out */ + + do { + /* try once without sleeping */ + if (count > 0) { + if (interval_us >= 1000) + msleep(interval_us/1000); + else + udelay(interval_us); + } + reg_val = dm_read_reg(ctx, addr); + field_value = get_reg_field_value_ex(reg_val, mask, shift); + count += interval_us; + + } while (field_value != condition_value && count <= timeout_us); + + ASSERT(count <= timeout_us); + + return count <= timeout_us; +} + +#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\ + wait_reg_func(\ + ctx,\ + mm##reg_name + inst_offset + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT,\ + condition_value,\ + 20000,\ + 200000) + +#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -254,6 +337,12 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dm_pp_notify_wm_clock_changes_soc15( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); +#endif + /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. -- cgit v1.2.3 From 8fa9ca2ec6919656db87391a1633692ee8d57c22 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:21:43 -0400 Subject: drm/amd/display: Remove DCE12 guards Signed-off-by: Jordan Lazare Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index bdc7cb045eed..cf6ecfcadd5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,7 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. @@ -274,7 +273,6 @@ static inline bool wait_reg_func( 20000,\ 200000) -#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -337,11 +335,9 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dm_pp_notify_wm_clock_changes_soc15( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); -#endif /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned -- cgit v1.2.3 From ff5ef99248662ef98a64c11c5370ecd9fbbf57a6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:27:42 -0400 Subject: drm/amdgpu/display: Enable DCN in DC Enable DCN in DC. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index cf6ecfcadd5e..fb61e333aefd 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -75,6 +75,10 @@ BREAK_TO_DEBUGGER(); \ } while (0) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include +#endif + #define dm_alloc(size) kzalloc(size, GFP_KERNEL) #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) #define dm_free(ptr) kfree(ptr) -- cgit v1.2.3 From daf6b57dd736ec93b2e1769b90514b015feed3c1 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 11 Jul 2017 13:48:17 -0400 Subject: drm/amd/display: add line number to reg_wait timeout print Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index fb61e333aefd..ea494a71a80b 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx, unsigned int generic_reg_wait(const struct dc_context *ctx, uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, - const char *func_name); + const char *func_name, int line); /* These macros need to be used with soc15 registers in order to retrieve -- cgit v1.2.3 From 2248eb6b4f1fdd7aded987d178a95b021d3a1d91 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 25 Jul 2017 22:52:45 -0400 Subject: drm/amd/display: log HUBP using DTN logging also simplify DTN INFO. all we need is a way to have DC log register states some where we can compare with golden. going through connectivity is overkill. Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index ea494a71a80b..e9bf4c417cc7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -463,4 +463,16 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) +/* + * Debug and verification hooks + */ +bool dm_helpers_dc_conn_log( + struct dc_context *ctx, + struct log_entry *entry, + enum dc_log_type event); + +void dm_dtn_log_begin(struct dc_context *ctx); +void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...); +void dm_dtn_log_end(struct dc_context *ctx); + #endif /* __DM_SERVICES_H__ */ -- cgit v1.2.3 From 43193c7991de7a2112fe2ddcfd930733bc357862 Mon Sep 17 00:00:00 2001 From: "AMD\\ktsao" Date: Sun, 30 Jul 2017 14:18:36 -0400 Subject: drm/amd/display: remove DCN1 guard as DCN1 is already open sourced. Signed-off-by: Kenny Tsao Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index e9bf4c417cc7..a7d661d1ff1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -75,9 +75,7 @@ BREAK_TO_DEBUGGER(); \ } while (0) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include -#endif #define dm_alloc(size) kzalloc(size, GFP_KERNEL) #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) -- cgit v1.2.3 From b4c8e6da39091b2931074e001febc598e2acdbb1 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 10 Aug 2017 16:16:20 -0400 Subject: drm/amd/display: Leave DCN config guard around fpu header See https://lists.freedesktop.org/archives/dri-devel/2017-August/149938.html Signed-off-by: Harry Wentland Reviewed-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index a7d661d1ff1d..e9bf4c417cc7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -75,7 +75,9 @@ BREAK_TO_DEBUGGER(); \ } while (0) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include +#endif #define dm_alloc(size) kzalloc(size, GFP_KERNEL) #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) -- cgit v1.2.3 From a185048ca88ce143f980f2b819f034cfc09a5377 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Sun, 13 Aug 2017 13:50:52 -0400 Subject: drm/amd/display: refactor pplib/smu communication new per SoC interface instead legacy interface with lots of un-used field that only cause confusion model pp_smu like one of our HW objects with func_ptr interface to call into it. struct pp_smu as handle to call pp/smu Signed-off-by: Tony Cheng Reviewed-by: Jun Lei Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index e9bf4c417cc7..8ab0af6f4c6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -339,9 +339,8 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); -bool dm_pp_notify_wm_clock_changes_soc15( - const struct dc_context *ctx, - struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); +void dm_pp_get_funcs_rv(struct dc_context *ctx, + struct pp_smu_funcs_rv *funcs); /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned -- cgit v1.2.3 From e9d7dc62bc09bd95461d5444b54d59195b207fd6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 28 Sep 2017 12:42:01 +1000 Subject: amdgpu/dc: don't check for 0 on register read/writes always. This adds ~50k to the driver text segment, and 10k to data segment. text data bss dec hex filename 2385556 39681 1045 2426282 2505aa drivers/gpu/drm/amd/amdgpu/amdgpu.o text data bss dec hex filename 2336593 28857 1045 2366495 241c1f drivers/gpu/drm/amd/amdgpu/amdgpu.o Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 8ab0af6f4c6b..c976e2aa10e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -96,6 +96,9 @@ irq_handler_idx dm_register_interrupt( * */ +/* enable for debugging new code, this adds 50k to the driver size. */ +/* #define DM_CHECK_ADDR_0 */ + #define dm_read_reg(ctx, address) \ dm_read_reg_func(ctx, address, __func__) @@ -105,12 +108,12 @@ static inline uint32_t dm_read_reg_func( const char *func_name) { uint32_t value; - +#ifdef DM_CHECK_ADDR_0 if (address == 0) { DC_ERR("invalid register read; address = 0\n"); return 0; } - +#endif value = cgs_read_register(ctx->cgs_device, address); return value; @@ -125,10 +128,12 @@ static inline void dm_write_reg_func( uint32_t value, const char *func_name) { +#ifdef DM_CHECK_ADDR_0 if (address == 0) { DC_ERR("invalid register write. address = 0"); return; } +#endif cgs_write_register(ctx->cgs_device, address, value); } -- cgit v1.2.3 From 29656a363c1f3060e9a5b3bafa0bd4b589e20e3c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 28 Sep 2017 13:29:32 +1000 Subject: amdgpu/dc: remove wait_reg/wait_reg_func interfaces. These aren't used in the tree anywhere, and there is a TODO. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 46 ---------------------------- 1 file changed, 46 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index c976e2aa10e0..8166027d2d83 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -236,52 +236,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) -/* TODO get rid of this pos*/ -static inline bool wait_reg_func( - const struct dc_context *ctx, - uint32_t addr, - uint32_t mask, - uint8_t shift, - uint32_t condition_value, - unsigned int interval_us, - unsigned int timeout_us) -{ - uint32_t field_value; - uint32_t reg_val; - unsigned int count = 0; - - if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) - timeout_us *= 655; /* 6553 give about 30 second before time out */ - - do { - /* try once without sleeping */ - if (count > 0) { - if (interval_us >= 1000) - msleep(interval_us/1000); - else - udelay(interval_us); - } - reg_val = dm_read_reg(ctx, addr); - field_value = get_reg_field_value_ex(reg_val, mask, shift); - count += interval_us; - - } while (field_value != condition_value && count <= timeout_us); - - ASSERT(count <= timeout_us); - - return count <= timeout_us; -} - -#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\ - wait_reg_func(\ - ctx,\ - mm##reg_name + inst_offset + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\ - reg_name ## __ ## reg_field ## _MASK,\ - reg_name ## __ ## reg_field ## __SHIFT,\ - condition_value,\ - 20000,\ - 200000) - /************************************** * Power Play (PP) interfaces **************************************/ -- cgit v1.2.3 From 4770b18493b3d9fe1f8913e69ec5134b103d5788 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 11 Oct 2017 12:42:30 -0400 Subject: drm/amd/display/dc: drop dm_delay_in_microseconds Use udelay directly. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 8166027d2d83..a11991c382de 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -404,9 +404,6 @@ bool dm_read_persistent_data(struct dc_context *ctx, unsigned int size, struct persistent_data_flag *flag); -void dm_delay_in_microseconds - (struct dc_context *ctx, unsigned int microSeconds); - bool dm_query_extended_brightness_caps (struct dc_context *ctx, enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps); -- cgit v1.2.3 From 215a6f05bcc18ffcd953a8527639ea1f571f4d81 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 6 Oct 2017 15:40:07 -0400 Subject: drm/amd/display: add performance trace macro to dc Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index a11991c382de..d6b3b832986b 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -418,6 +418,8 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) +unsigned long long dm_get_timestamp(struct dc_context *ctx); + /* * Debug and verification hooks */ -- cgit v1.2.3 From 75e68891200e3404fb3283e47ed74184932a748a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 12 Oct 2017 12:27:48 -0400 Subject: drm/amd/display: Move OS types to os_types.h Some of this stuff is not really dm_services Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 45 ---------------------------- 1 file changed, 45 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index d6b3b832986b..c8190c38a644 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -38,51 +38,6 @@ #undef DEPRECATED -/* - * - * general debug capabilities - * - */ -#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER) - -#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) -#define ASSERT_CRITICAL(expr) do { \ - if (WARN_ON(!(expr))) { \ - kgdb_breakpoint(); \ - } \ -} while (0) -#else -#define ASSERT_CRITICAL(expr) do { \ - if (WARN_ON(!(expr))) { \ - ; \ - } \ -} while (0) -#endif - -#if defined(CONFIG_DEBUG_KERNEL_DC) -#define ASSERT(expr) ASSERT_CRITICAL(expr) - -#else -#define ASSERT(expr) WARN_ON(!(expr)) -#endif - -#define BREAK_TO_DEBUGGER() ASSERT(0) - -#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */ - -#define DC_ERR(...) do { \ - dm_error(__VA_ARGS__); \ - BREAK_TO_DEBUGGER(); \ -} while (0) - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -#include -#endif - -#define dm_alloc(size) kzalloc(size, GFP_KERNEL) -#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) -#define dm_free(ptr) kfree(ptr) - irq_handler_idx dm_register_interrupt( struct dc_context *ctx, struct dc_interrupt_params *int_params, -- cgit v1.2.3 From d8d46ae97ffd4ace4b8a7f45c232ff4bb8b6c129 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 12:26:42 +0100 Subject: drm/amdgpu/display: remove unused REG_OFFSET macro The name conflicts with another macro of the same name on the ARM ixp4xx platform, leading to build errors. Neither of the users actually should use a name that generic, but the other one was here first and the dc driver doesn't actually use it. Reviewed-by: Harry Wentland Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dm_services.h') diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index c8190c38a644..d4917037ac42 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -160,9 +160,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. */ -#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) -#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) - #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) -- cgit v1.2.3