From 338a95a95508537e23c82d59a2d87be6fde4b6ff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jul 2013 15:14:25 -0400 Subject: drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag Some asic revisions need to disable PG when UVD is active. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/sumo_dpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/radeon/sumo_dpm.c') diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index b13448f13ee8..dc599060a9a4 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev, radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); if (pi->enable_gfx_power_gating) { - sumo_gfx_powergating_enable(rdev, true); + if (!pi->disable_gfx_power_gating_in_uvd || + !r600_is_uvd_state(new_rps->class, new_rps->class2)) + sumo_gfx_powergating_enable(rdev, true); } } -- cgit v1.2.3