From 3c699105d0376c14940ce7cf561754a94cdff8dd Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Tue, 21 Jan 2014 16:23:01 -0500 Subject: mfd: Delete non-required instances of include None of these files are actually using any __init type directives and hence don't need to include . Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index be93fa261ded..010c1b490478 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -58,7 +58,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include #include #include #include -- cgit v1.2.3 From facd9939403cb5769190054a600474399e776e3a Mon Sep 17 00:00:00 2001 From: Vincent Donnefort Date: Fri, 14 Feb 2014 15:01:54 +0100 Subject: mfd: lpc_ich: Add support for Intel Avoton GPIOs Signed-off-by: Vincent Donnefort Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 010c1b490478..17eff0925ac1 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -499,6 +499,7 @@ static struct lpc_ich_info lpc_chipset_info[] = { [LPC_AVN] = { .name = "Avoton SoC", .iTCO_version = 1, + .gpio_version = AVOTON_GPIO, }, [LPC_COLETO] = { .name = "Coleto Creek", -- cgit v1.2.3 From f5dccb15877b82a40950c6f752d5345c86189fc9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:51 -0500 Subject: mfd: lpc_ich: Fix ACPI enable bitmask The original bitmask of 0x10 was incorrect and would result in a write to a reserved read-only bit instead of enabling the ACPI I/O region. Update it to the proper value of 0x80. Signed-off-by: Peter Tyser Tested-by: Rajat Jain Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 17eff0925ac1..2be85a4b36c0 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -759,7 +759,7 @@ static void lpc_ich_enable_acpi_space(struct pci_dev *dev) u8 reg_save; pci_read_config_byte(dev, priv->acpi.ctrl, ®_save); - pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10); + pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x80); priv->acpi.save = reg_save; } -- cgit v1.2.3 From f0776b8ce03ceb638c51b62f324844c71c446600 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:52 -0500 Subject: mfd: lpc_ich: Only configure watchdog or GPIO when present Some chipsets don't currently have GPIO support enabled. For these chipsets don't go through the process of initializing the GPIO region. Make the same change for the watchdog initialization for chipsets which may not enable the WDT in the future. Signed-off-by: Peter Tyser Tested-by: Rajat Jain Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 2be85a4b36c0..cffa8367ddcf 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -967,13 +967,17 @@ static int lpc_ich_probe(struct pci_dev *dev, pci_set_drvdata(dev, priv); - ret = lpc_ich_init_wdt(dev); - if (!ret) - cell_added = true; + if (lpc_chipset_info[priv->chipset].iTCO_version) { + ret = lpc_ich_init_wdt(dev); + if (!ret) + cell_added = true; + } - ret = lpc_ich_init_gpio(dev); - if (!ret) - cell_added = true; + if (lpc_chipset_info[priv->chipset].gpio_version) { + ret = lpc_ich_init_gpio(dev); + if (!ret) + cell_added = true; + } /* * We only care if at least one or none of the cells registered -- cgit v1.2.3 From 429b941abd503c8936e116c819362323aafdbd50 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:53 -0500 Subject: mfd: lpc_ich: Remove lpc_ich_cfg struct use Future chipsets will use different register layouts that don't map cleanly to the lpc_ich_cfg fields. Remove the lpc_ich_cfg struct and add explicit fields to the higher level lpc_ich_priv structure. This change should have no functional impact. Signed-off-by: Peter Tyser Tested-by: Rajat Jain Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 63 ++++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 31 deletions(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index cffa8367ddcf..b24bae2bcdea 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -89,16 +89,16 @@ #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) -struct lpc_ich_cfg { - int base; - int ctrl; - int save; -}; - struct lpc_ich_priv { int chipset; - struct lpc_ich_cfg acpi; - struct lpc_ich_cfg gpio; + + int abase; /* ACPI base */ + int actrl; /* ACPI control or PMC base */ + int gbase; /* GPIO base */ + int gctrl; /* GPIO control */ + + int actrl_save; /* Cached ACPI control base value */ + int gctrl_save; /* Cached GPIO control value */ }; static struct resource wdt_ich_res[] = { @@ -742,14 +742,14 @@ static void lpc_ich_restore_config_space(struct pci_dev *dev) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); - if (priv->acpi.save >= 0) { - pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save); - priv->acpi.save = -1; + if (priv->actrl_save >= 0) { + pci_write_config_byte(dev, priv->actrl, priv->actrl_save); + priv->actrl_save = -1; } - if (priv->gpio.save >= 0) { - pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save); - priv->gpio.save = -1; + if (priv->gctrl_save >= 0) { + pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); + priv->gctrl_save = -1; } } @@ -758,9 +758,9 @@ static void lpc_ich_enable_acpi_space(struct pci_dev *dev) struct lpc_ich_priv *priv = pci_get_drvdata(dev); u8 reg_save; - pci_read_config_byte(dev, priv->acpi.ctrl, ®_save); - pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x80); - priv->acpi.save = reg_save; + pci_read_config_byte(dev, priv->actrl, ®_save); + pci_write_config_byte(dev, priv->actrl, reg_save | 0x80); + priv->actrl_save = reg_save; } static void lpc_ich_enable_gpio_space(struct pci_dev *dev) @@ -768,9 +768,9 @@ static void lpc_ich_enable_gpio_space(struct pci_dev *dev) struct lpc_ich_priv *priv = pci_get_drvdata(dev); u8 reg_save; - pci_read_config_byte(dev, priv->gpio.ctrl, ®_save); - pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10); - priv->gpio.save = reg_save; + pci_read_config_byte(dev, priv->gctrl, ®_save); + pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); + priv->gctrl_save = reg_save; } static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell) @@ -815,7 +815,7 @@ static int lpc_ich_init_gpio(struct pci_dev *dev) struct resource *res; /* Setup power management base register */ - pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); + pci_read_config_dword(dev, priv->abase, &base_addr_cfg); base_addr = base_addr_cfg & 0x0000ff80; if (!base_addr) { dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); @@ -841,7 +841,7 @@ static int lpc_ich_init_gpio(struct pci_dev *dev) gpe0_done: /* Setup GPIO base register */ - pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg); + pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); base_addr = base_addr_cfg & 0x0000ff80; if (!base_addr) { dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); @@ -891,7 +891,7 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) struct resource *res; /* Setup power management base register */ - pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); + pci_read_config_dword(dev, priv->abase, &base_addr_cfg); base_addr = base_addr_cfg & 0x0000ff80; if (!base_addr) { dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); @@ -952,17 +952,18 @@ static int lpc_ich_probe(struct pci_dev *dev, return -ENOMEM; priv->chipset = id->driver_data; - priv->acpi.save = -1; - priv->acpi.base = ACPIBASE; - priv->acpi.ctrl = ACPICTRL; - priv->gpio.save = -1; + priv->actrl_save = -1; + priv->abase = ACPIBASE; + priv->actrl = ACPICTRL; + + priv->gctrl_save = -1; if (priv->chipset <= LPC_ICH5) { - priv->gpio.base = GPIOBASE_ICH0; - priv->gpio.ctrl = GPIOCTRL_ICH0; + priv->gbase = GPIOBASE_ICH0; + priv->gctrl = GPIOCTRL_ICH0; } else { - priv->gpio.base = GPIOBASE_ICH6; - priv->gpio.ctrl = GPIOCTRL_ICH6; + priv->gbase = GPIOBASE_ICH6; + priv->gctrl = GPIOCTRL_ICH6; } pci_set_drvdata(dev, priv); -- cgit v1.2.3 From eb71d4dec4a5e010e34b9d7afdb5af41884c388e Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:54 -0500 Subject: mfd: lpc_ich: Add support for iTCO v3 Some newer Atom CPUs, eg Avoton and Bay Trail, use slightly different register layouts for the iTCO than the current v1 and v2 iTCO. Differences from previous iTCO versions include: - The ACPI space is enabled in the "ACPI base address" register instead of the "ACPI control register" - The "no reboot" functionality is set in the "Power Management Configuration" register instead of the "General Control and Status" (GCS) register or PCI configuration space. - The "ACPI Control Register" is not present on v3. The "Power Management Configuration Base Address" register resides at the same address is Avoton/Bay Trail. To differentiate these newer chipsets create a new v3 iTCO version and update the MFD driver to support them. Signed-off-by: Peter Tyser Tested-by: Rajat Jain Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 81 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 67 insertions(+), 14 deletions(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index b24bae2bcdea..c0683370abbf 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -71,9 +71,11 @@ #define ACPIBASE_GPE_END 0x2f #define ACPIBASE_SMI_OFF 0x30 #define ACPIBASE_SMI_END 0x33 +#define ACPIBASE_PMC_OFF 0x08 +#define ACPIBASE_PMC_END 0x0c #define ACPIBASE_TCO_OFF 0x60 #define ACPIBASE_TCO_END 0x7f -#define ACPICTRL 0x44 +#define ACPICTRL_PMCBASE 0x44 #define ACPIBASE_GCS_OFF 0x3410 #define ACPIBASE_GCS_END 0x3414 @@ -93,11 +95,12 @@ struct lpc_ich_priv { int chipset; int abase; /* ACPI base */ - int actrl; /* ACPI control or PMC base */ + int actrl_pbase; /* ACPI control or PMC base */ int gbase; /* GPIO base */ int gctrl; /* GPIO control */ - int actrl_save; /* Cached ACPI control base value */ + int abase_save; /* Cached ACPI base value */ + int actrl_pbase_save; /* Cached ACPI control or PMC base value */ int gctrl_save; /* Cached GPIO control value */ }; @@ -110,7 +113,7 @@ static struct resource wdt_ich_res[] = { { .flags = IORESOURCE_IO, }, - /* GCS */ + /* GCS or PMC */ { .flags = IORESOURCE_MEM, }, @@ -742,9 +745,15 @@ static void lpc_ich_restore_config_space(struct pci_dev *dev) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); - if (priv->actrl_save >= 0) { - pci_write_config_byte(dev, priv->actrl, priv->actrl_save); - priv->actrl_save = -1; + if (priv->abase_save >= 0) { + pci_write_config_byte(dev, priv->abase, priv->abase_save); + priv->abase_save = -1; + } + + if (priv->actrl_pbase_save >= 0) { + pci_write_config_byte(dev, priv->actrl_pbase, + priv->actrl_pbase_save); + priv->actrl_pbase_save = -1; } if (priv->gctrl_save >= 0) { @@ -758,9 +767,26 @@ static void lpc_ich_enable_acpi_space(struct pci_dev *dev) struct lpc_ich_priv *priv = pci_get_drvdata(dev); u8 reg_save; - pci_read_config_byte(dev, priv->actrl, ®_save); - pci_write_config_byte(dev, priv->actrl, reg_save | 0x80); - priv->actrl_save = reg_save; + switch (lpc_chipset_info[priv->chipset].iTCO_version) { + case 3: + /* + * Some chipsets (eg Avoton) enable the ACPI space in the + * ACPI BASE register. + */ + pci_read_config_byte(dev, priv->abase, ®_save); + pci_write_config_byte(dev, priv->abase, reg_save | 0x2); + priv->abase_save = reg_save; + break; + default: + /* + * Most chipsets enable the ACPI space in the ACPI control + * register. + */ + pci_read_config_byte(dev, priv->actrl_pbase, ®_save); + pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); + priv->actrl_pbase_save = reg_save; + break; + } } static void lpc_ich_enable_gpio_space(struct pci_dev *dev) @@ -773,6 +799,17 @@ static void lpc_ich_enable_gpio_space(struct pci_dev *dev) priv->gctrl_save = reg_save; } +static void lpc_ich_enable_pmc_space(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u8 reg_save; + + pci_read_config_byte(dev, priv->actrl_pbase, ®_save); + pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); + + priv->actrl_pbase_save = reg_save; +} + static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); @@ -910,14 +947,20 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) lpc_ich_enable_acpi_space(dev); /* + * iTCO v2: * Get the Memory-Mapped GCS register. To get access to it * we have to read RCBA from PCI Config space 0xf0 and use * it as base. GCS = RCBA + ICH6_GCS(0x3410). + * + * iTCO v3: + * Get the Power Management Configuration register. To get access + * to it we have to read the PMC BASE from config space and address + * the register at offset 0x8. */ if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { /* Don't register iomem for TCO ver 1 */ lpc_ich_cells[LPC_WDT].num_resources--; - } else { + } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); base_addr = base_addr_cfg & 0xffffc000; if (!(base_addr_cfg & 1)) { @@ -926,9 +969,17 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) ret = -ENODEV; goto wdt_done; } - res = wdt_mem_res(ICH_RES_MEM_GCS); + res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); res->start = base_addr + ACPIBASE_GCS_OFF; res->end = base_addr + ACPIBASE_GCS_END; + } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { + lpc_ich_enable_pmc_space(dev); + pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); + base_addr = base_addr_cfg & 0xfffffe00; + + res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); + res->start = base_addr + ACPIBASE_PMC_OFF; + res->end = base_addr + ACPIBASE_PMC_END; } lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]); @@ -953,9 +1004,11 @@ static int lpc_ich_probe(struct pci_dev *dev, priv->chipset = id->driver_data; - priv->actrl_save = -1; + priv->actrl_pbase_save = -1; + priv->abase_save = -1; + priv->abase = ACPIBASE; - priv->actrl = ACPICTRL; + priv->actrl_pbase = ACPICTRL_PMCBASE; priv->gctrl_save = -1; if (priv->chipset <= LPC_ICH5) { -- cgit v1.2.3 From c48cf59878685cc06b71bb2a3ca17b61103c8de7 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:56 -0500 Subject: mfd: lpc_ich: Change Avoton to iTCO v3 The register layout of the Avoton is compatible with the iTCO v3 register layout. Signed-off-by: Peter Tyser Tested-by: Rajat Jain Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index c0683370abbf..b201b0d893ca 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -501,7 +501,7 @@ static struct lpc_ich_info lpc_chipset_info[] = { }, [LPC_AVN] = { .name = "Avoton SoC", - .iTCO_version = 1, + .iTCO_version = 3, .gpio_version = AVOTON_GPIO, }, [LPC_COLETO] = { -- cgit v1.2.3 From 117bbfe25cfc2e968be1f7976ac460a5cd3d734e Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:57 -0500 Subject: mfd: lpc_ich: Add support for NM10 GPIO The NM10's GPIO is compatible with ICH v7 GPIO. Signed-off-by: Peter Tyser Tested-by: Dan Weinlader Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index b201b0d893ca..2f657c7472b2 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -305,6 +305,7 @@ static struct lpc_ich_info lpc_chipset_info[] = { [LPC_NM10] = { .name = "NM10", .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, }, [LPC_ICH8] = { .name = "ICH8 or ICH8R", -- cgit v1.2.3 From 6111ec70357022ccd037399c13f69900431850b4 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 10 Mar 2014 16:34:58 -0500 Subject: mfd: lpc_ich: Add support for Intel Bay Trail SoC This patch adds the LPC Controller Device IDs for Watchdog and GPIO for the Intel Bay Trail Atom SoC. Signed-off-by: Peter Tyser Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/mfd/lpc_ich.c') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 2f657c7472b2..3f10ea3f45d1 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -213,6 +213,7 @@ enum lpc_chipsets { LPC_LPT_LP, /* Lynx Point-LP */ LPC_WBG, /* Wellsburg */ LPC_AVN, /* Avoton SoC */ + LPC_BAYTRAIL, /* Bay Trail SoC */ LPC_COLETO, /* Coleto Creek */ LPC_WPT_LP, /* Wildcat Point-LP */ }; @@ -505,6 +506,10 @@ static struct lpc_ich_info lpc_chipset_info[] = { .iTCO_version = 3, .gpio_version = AVOTON_GPIO, }, + [LPC_BAYTRAIL] = { + .name = "Bay Trail SoC", + .iTCO_version = 3, + }, [LPC_COLETO] = { .name = "Coleto Creek", .iTCO_version = 2, @@ -730,6 +735,7 @@ static const struct pci_device_id lpc_ich_ids[] = { { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, + { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, -- cgit v1.2.3