From e0c7d7675331140e5186d2d1a0efce1d3877d379 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Sat, 13 May 2006 18:07:53 +0100 Subject: [MTD NAND] Indent all of drivers/mtd/nand/*.c. It was just too painful to deal with. Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 143 ++++++++++++++++++++++---------------------- 1 file changed, 73 insertions(+), 70 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index bde3550910a2..50cbfd4826fb 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -38,22 +38,20 @@ */ static struct mtd_info *au1550_mtd = NULL; static void __iomem *p_nand; -static int nand_width = 1; /* default x8*/ +static int nand_width = 1; /* default x8 */ /* * Define partitions for flash device */ static const struct mtd_partition partition_info[] = { { - .name = "NAND FS 0", - .offset = 0, - .size = 8*1024*1024 - }, + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024}, { - .name = "NAND FS 1", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL - } + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL} }; /** @@ -157,7 +155,7 @@ static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) int i; struct nand_chip *this = mtd->priv; - for (i=0; iIO_ADDR_W); au_sync(); } @@ -176,7 +174,7 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) int i; struct nand_chip *this = mtd->priv; - for (i=0; iIO_ADDR_R); au_sync(); } @@ -195,7 +193,7 @@ static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) int i; struct nand_chip *this = mtd->priv; - for (i=0; iIO_ADDR_R)) return -EFAULT; au_sync(); @@ -219,7 +217,7 @@ static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) u16 *p = (u16 *) buf; len >>= 1; - for (i=0; iIO_ADDR_W); au_sync(); } @@ -241,7 +239,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) u16 *p = (u16 *) buf; len >>= 1; - for (i=0; iIO_ADDR_R); au_sync(); } @@ -262,7 +260,7 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) u16 *p = (u16 *) buf; len >>= 1; - for (i=0; iIO_ADDR_R)) return -EFAULT; au_sync(); @@ -275,27 +273,35 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) { register struct nand_chip *this = mtd->priv; - switch(cmd){ + switch (cmd) { + + case NAND_CTL_SETCLE: + this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; + break; + + case NAND_CTL_CLRCLE: + this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; + break; - case NAND_CTL_SETCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; break; - case NAND_CTL_CLRCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; break; + case NAND_CTL_SETALE: + this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; + break; - case NAND_CTL_SETALE: this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; break; case NAND_CTL_CLRALE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; - /* FIXME: Nobody knows why this is neccecary, + /* FIXME: Nobody knows why this is necessary, * but it works only that way */ udelay(1); break; case NAND_CTL_SETNCE: /* assert (force assert) chip enable */ - au_writel((1<<(4+NAND_CS)) , MEM_STNDCTL); break; + au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); break; case NAND_CTL_CLRNCE: - /* deassert chip enable */ - au_writel(0, MEM_STNDCTL); break; + /* deassert chip enable */ + au_writel(0, MEM_STNDCTL); break; } @@ -315,66 +321,63 @@ int au1550_device_ready(struct mtd_info *mtd) /* * Main initialization routine */ -int __init au1xxx_nand_init (void) +int __init au1xxx_nand_init(void) { struct nand_chip *this; - u16 boot_swapboot = 0; /* default value */ + u16 boot_swapboot = 0; /* default value */ int retval; u32 mem_staddr; u32 nand_phys; /* Allocate memory for MTD device structure and private data */ - au1550_mtd = kmalloc (sizeof(struct mtd_info) + - sizeof (struct nand_chip), GFP_KERNEL); + au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); if (!au1550_mtd) { - printk ("Unable to allocate NAND MTD dev structure.\n"); + printk("Unable to allocate NAND MTD dev structure.\n"); return -ENOMEM; } /* Get pointer to private data */ - this = (struct nand_chip *) (&au1550_mtd[1]); + this = (struct nand_chip *)(&au1550_mtd[1]); /* Initialize structures */ - memset((char *) au1550_mtd, 0, sizeof(struct mtd_info)); - memset((char *) this, 0, sizeof(struct nand_chip)); + memset(au1550_mtd, 0, sizeof(struct mtd_info)); + memset(this, 0, sizeof(struct nand_chip)); /* Link the private data with the MTD structure */ au1550_mtd->priv = this; - /* disable interrupts */ - au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL); + au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL); /* disable NAND boot */ - au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL); + au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL); #ifdef CONFIG_MIPS_PB1550 /* set gpio206 high */ - au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR); + au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); - boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) | - ((bcsr->status >> 6) & 0x1); + boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1); switch (boot_swapboot) { - case 0: - case 2: - case 8: - case 0xC: - case 0xD: - /* x16 NAND Flash */ - nand_width = 0; - break; - case 1: - case 9: - case 3: - case 0xE: - case 0xF: - /* x8 NAND Flash */ - nand_width = 1; - break; - default: - printk("Pb1550 NAND: bad boot:swap\n"); - retval = -EINVAL; - goto outmem; + case 0: + case 2: + case 8: + case 0xC: + case 0xD: + /* x16 NAND Flash */ + nand_width = 0; + break; + case 1: + case 9: + case 3: + case 0xE: + case 0xF: + /* x8 NAND Flash */ + nand_width = 1; + break; + default: + printk("Pb1550 NAND: bad boot:swap\n"); + retval = -EINVAL; + goto outmem; } #endif @@ -424,14 +427,13 @@ int __init au1xxx_nand_init (void) /* make controller and MTD agree */ if (NAND_CS == 0) - nand_width = au_readl(MEM_STCFG0) & (1<<22); + nand_width = au_readl(MEM_STCFG0) & (1 << 22); if (NAND_CS == 1) - nand_width = au_readl(MEM_STCFG1) & (1<<22); + nand_width = au_readl(MEM_STCFG1) & (1 << 22); if (NAND_CS == 2) - nand_width = au_readl(MEM_STCFG2) & (1<<22); + nand_width = au_readl(MEM_STCFG2) & (1 << 22); if (NAND_CS == 3) - nand_width = au_readl(MEM_STCFG3) & (1<<22); - + nand_width = au_readl(MEM_STCFG3) & (1 << 22); /* Set address of hardware control function */ this->hwcontrol = au1550_hwcontrol; @@ -454,7 +456,7 @@ int __init au1xxx_nand_init (void) this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; /* Scan to find existence of the device */ - if (nand_scan (au1550_mtd, 1)) { + if (nand_scan(au1550_mtd, 1)) { retval = -ENXIO; goto outio; } @@ -465,10 +467,10 @@ int __init au1xxx_nand_init (void) return 0; outio: - iounmap ((void *)p_nand); + iounmap((void *)p_nand); outmem: - kfree (au1550_mtd); + kfree(au1550_mtd); return retval; } @@ -478,19 +480,20 @@ module_init(au1xxx_nand_init); * Clean up routine */ #ifdef MODULE -static void __exit au1550_cleanup (void) +static void __exit au1550_cleanup(void) { - struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1]; + struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1]; /* Release resources, unregister device */ - nand_release (au1550_mtd); + nand_release(au1550_mtd); /* Free the MTD device structure */ - kfree (au1550_mtd); + kfree(au1550_mtd); /* Unmap */ - iounmap ((void *)p_nand); + iounmap((void *)p_nand); } + module_exit(au1550_cleanup); #endif -- cgit v1.2.3 From 552d9205186428a1e2a49ed577bcbba9f777af37 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Sun, 14 May 2006 01:20:46 +0100 Subject: [MTD] Fix module refcounting in NAND board drivers. The _board_ driver needs to be mtd->owner, and it in turn pins the nand.ko module. Fix them all to actually do that, and fix nand.ko not to overwrite it -- and also to check that the caller sets it, if the caller is a module. Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 50cbfd4826fb..87d34351a86d 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -345,6 +345,7 @@ int __init au1xxx_nand_init(void) /* Link the private data with the MTD structure */ au1550_mtd->priv = this; + au1550_mtd->owner = THIS_MODULE; /* disable interrupts */ au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL); -- cgit v1.2.3 From cead4dbc03ba6eb2e35bac04439b76a0cc2286ce Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 16 May 2006 13:54:50 +0100 Subject: [MTD NAND] Make various initfuncs static, remove #ifdef MODULE from exitfuncs We all inherited the same error from the original NAND board driver which got copied and changed. Fix them all at once... Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 87d34351a86d..861fb961d942 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -321,7 +321,7 @@ int au1550_device_ready(struct mtd_info *mtd) /* * Main initialization routine */ -int __init au1xxx_nand_init(void) +static int __init au1xxx_nand_init(void) { struct nand_chip *this; u16 boot_swapboot = 0; /* default value */ @@ -480,7 +480,6 @@ module_init(au1xxx_nand_init); /* * Clean up routine */ -#ifdef MODULE static void __exit au1550_cleanup(void) { struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1]; @@ -496,7 +495,6 @@ static void __exit au1550_cleanup(void) } module_exit(au1550_cleanup); -#endif MODULE_LICENSE("GPL"); MODULE_AUTHOR("Embedded Edge, LLC"); -- cgit v1.2.3 From 155285c4775b7027b01a5b744c721ae43cced798 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 16 May 2006 20:16:41 +0400 Subject: NAND: AMD Au1550 driver reads write-only register During the last cleanup of the AMD Au1550 NAND driver the old buglet was reintroduced: as the MEM_STNDCTL register is write-only and seem to always read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus possibly causing a contention on the static bus when the NOR flash (using -RCS0) or board control status registers (using -RCS2) are read. Luckily, this goes away with a first NAND access, since au1550_hwcontrol() doesn't try to read this register before writing anymore. Signed-off-by: Sergei Shtylyov Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 861fb961d942..839b35a386b6 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -347,11 +347,9 @@ static int __init au1xxx_nand_init(void) au1550_mtd->priv = this; au1550_mtd->owner = THIS_MODULE; - /* disable interrupts */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL); - /* disable NAND boot */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL); + /* MEM_STNDCTL: disable ints, disable nand boot */ + au_writel(0, MEM_STNDCTL); #ifdef CONFIG_MIPS_PB1550 /* set gpio206 high */ -- cgit v1.2.3 From 35af68b53a62c98bf551aaae7be179bde248eb34 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 16 May 2006 20:52:06 +0400 Subject: NAND: Fix NAND ECC errors on AMD Au1550 On AMD Au1550 the static bus controller fails to keep -CE asserted during chip ready delay on read commands and the NAND chip being used requires this. So, the current driver allows nand_base.c to drive -CE manually during the entire sector read. When the PCMCIA driver is enabled however, occasionally the ECC errors occur on NAND reads. This happens because the PCMCIA driver polls sockets periodically and reads one of the board's control/status regs (BCSRs) which are on the same static bus as the NAND flash, and just use another chip select (and the NOR flash also resides on that bus), so as the NAND driver forces NAND chip select asserted and the -RE signal is shared, a contention occurs on the static bus when BCSR or NOR flash is read while we're reading from NAND. So, we either can't keep interrupts enabled during the whole NAND sector read (which is hardly acceptable), or have to implement some interlocking scheme between multiple drivers (which is painful, and makes me shudder :-). There's a third way which has proven to work: to force -CE asserted only while we're waiting for a NAND chip to become ready after a read command, disabling interrupts for a maximum of 25 microseconds (according to Toshiba TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics); for Samsung NAND chip which seems to be actually used this delay is even less, 12 us. Signed-off-by: Konstantin Baydarov Signed-off-by: Sergei Shtylyov Signed-off-by: David Woodhouse --- drivers/mtd/nand/au1550nd.c | 139 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 839b35a386b6..d9a0143e1d3a 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -318,6 +319,141 @@ int au1550_device_ready(struct mtd_info *mtd) return ret; } +/** + * au1550_select_chip - control -CE line + * Forbid driving -CE manually permitting the NAND controller to do this. + * Keeping -CE asserted during the whole sector reads interferes with the + * NOR flash and PCMCIA drivers as it causes contention on the static bus. + * We only have to hold -CE low for the NAND read commands since the flash + * chip needs it to be asserted during chip not ready time but the NAND + * controller keeps it released. + * + * @mtd: MTD device structure + * @chip: chipnumber to select, -1 for deselect + */ +static void au1550_select_chip(struct mtd_info *mtd, int chip) +{ +} + +/** + * au1550_command - Send command to NAND device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + */ +static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + int ce_override = 0, i; + ulong flags; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + this->write_byte(mtd, readcmd); + } + this->write_byte(mtd, command); + + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column); + } + if (page_addr != -1) { + this->write_byte(mtd, (u8)(page_addr & 0xff)); + + if (command == NAND_CMD_READ0 || + command == NAND_CMD_READ1 || + command == NAND_CMD_READOOB) { + /* + * NAND controller will release -CE after + * the last address byte is written, so we'll + * have to forcibly assert it. No interrupts + * are allowed while we do this as we don't + * want the NOR flash or PCMCIA drivers to + * steal our precious bytes of data... + */ + ce_override = 1; + local_irq_save(flags); + this->hwcontrol(mtd, NAND_CTL_SETNCE); + } + + this->write_byte(mtd, (u8)(page_addr >> 8)); + + /* One more address cycle for devices > 32MiB */ + if (this->chipsize > (32 << 20)) + this->write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * Program and erase have their own busy handlers. + * Status and sequential in need no delay. + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + break; + + case NAND_CMD_READ0: + case NAND_CMD_READ1: + case NAND_CMD_READOOB: + /* Check if we're really driving -CE low (just in case) */ + if (unlikely(!ce_override)) + break; + + /* Apply a short delay always to ensure that we do wait tWB. */ + ndelay(100); + /* Wait for a chip to become ready... */ + for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) + udelay(1); + + /* Release -CE and re-enable interrupts. */ + this->hwcontrol(mtd, NAND_CTL_CLRNCE); + local_irq_restore(flags); + return; + } + /* Apply this short delay always to ensure that we do wait tWB. */ + ndelay(100); + + while(!this->dev_ready(mtd)); +} + + /* * Main initialization routine */ @@ -437,6 +573,9 @@ static int __init au1xxx_nand_init(void) /* Set address of hardware control function */ this->hwcontrol = au1550_hwcontrol; this->dev_ready = au1550_device_ready; + this->select_chip = au1550_select_chip; + this->cmdfunc = au1550_command; + /* 30 us command delay time */ this->chip_delay = 30; this->eccmode = NAND_ECC_SOFT; -- cgit v1.2.3 From 28318776a80bc3261f9af91ef79e6e38bb9f5bec Mon Sep 17 00:00:00 2001 From: Joern Engel Date: Mon, 22 May 2006 23:18:05 +0200 Subject: [MTD] Introduce writesize At least two flashes exists that have the concept of a minimum write unit, similar to NAND pages, but no other NAND characteristics. Therefore, rename the minimum write unit to "writesize" for all flashes, including NAND. Signed-off-by: Joern Engel --- drivers/mtd/nand/au1550nd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index d9a0143e1d3a..4253b9309789 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -356,9 +356,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i if (command == NAND_CMD_SEQIN) { int readcmd; - if (column >= mtd->oobblock) { + if (column >= mtd->writesize) { /* OOB area */ - column -= mtd->oobblock; + column -= mtd->writesize; readcmd = NAND_CMD_READOOB; } else if (column < 256) { /* First 256 bytes --> READ0 */ -- cgit v1.2.3 From 6dfc6d250d0b7ebaa6423c44dcd09fcfe68deabd Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 May 2006 12:00:46 +0200 Subject: [MTD] NAND modularize ECC First step of modularizing ECC support. - Move ECC related functionality into a seperate embedded data structure - Get rid of the hardware dependend constants to simplify new ECC models Signed-off-by: Thomas Gleixner --- drivers/mtd/nand/au1550nd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index d9a0143e1d3a..d7f04abfe18e 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -578,7 +578,7 @@ static int __init au1xxx_nand_init(void) /* 30 us command delay time */ this->chip_delay = 30; - this->eccmode = NAND_ECC_SOFT; + this->ecc.mode = NAND_ECC_SOFT; this->options = NAND_NO_AUTOINCR; -- cgit v1.2.3 From 7abd3ef9875eb2afcdcd4f450680298a2983a55e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 May 2006 23:25:53 +0200 Subject: [MTD] Refactor NAND hwcontrol to cmd_ctrl The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner --- drivers/mtd/nand/au1550nd.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 29dde7dcafa1..275453ea7a71 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -269,6 +269,18 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) return 0; } +/* Select the chip by setting nCE to low */ +#define NAND_CTL_SETNCE 1 +/* Deselect the chip by setting nCE to high */ +#define NAND_CTL_CLRNCE 2 +/* Select the command latch by setting CLE to high */ +#define NAND_CTL_SETCLE 3 +/* Deselect the command latch by setting CLE to low */ +#define NAND_CTL_CLRCLE 4 +/* Select the address latch by setting ALE to high */ +#define NAND_CTL_SETALE 5 +/* Deselect the address latch by setting ALE to low */ +#define NAND_CTL_CLRALE 6 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) { @@ -349,7 +361,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i ulong flags; /* Begin command latch cycle */ - this->hwcontrol(mtd, NAND_CTL_SETCLE); + au1550_hwcontrol(mtd, NAND_CTL_SETCLE); /* * Write out the command to the device. */ @@ -372,10 +384,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i this->write_byte(mtd, command); /* Set ALE and clear CLE to start address cycle */ - this->hwcontrol(mtd, NAND_CTL_CLRCLE); + au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); if (column != -1 || page_addr != -1) { - this->hwcontrol(mtd, NAND_CTL_SETALE); + au1550_hwcontrol(mtd, NAND_CTL_SETALE); /* Serially input address */ if (column != -1) { @@ -400,7 +412,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i */ ce_override = 1; local_irq_save(flags); - this->hwcontrol(mtd, NAND_CTL_SETNCE); + au1550_hwcontrol(mtd, NAND_CTL_SETNCE); } this->write_byte(mtd, (u8)(page_addr >> 8)); @@ -410,7 +422,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i this->write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); } /* Latch in address */ - this->hwcontrol(mtd, NAND_CTL_CLRALE); + au1550_hwcontrol(mtd, NAND_CTL_CLRALE); } /* @@ -443,7 +455,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i udelay(1); /* Release -CE and re-enable interrupts. */ - this->hwcontrol(mtd, NAND_CTL_CLRNCE); + au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); local_irq_restore(flags); return; } @@ -571,7 +583,6 @@ static int __init au1xxx_nand_init(void) nand_width = au_readl(MEM_STCFG3) & (1 << 22); /* Set address of hardware control function */ - this->hwcontrol = au1550_hwcontrol; this->dev_ready = au1550_device_ready; this->select_chip = au1550_select_chip; this->cmdfunc = au1550_command; -- cgit v1.2.3 From cad74f2c380411ae7bee997f3ba18834cfe313a2 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 23 May 2006 23:28:48 +0200 Subject: [MTD] NAND remove write_byte/word function from nand_chip The previous change of the command / hardware control allows to remove the write_byte/word functions completely, as their only user were nand_command and nand_command_lp. Signed-off-by: Thomas Gleixner --- drivers/mtd/nand/au1550nd.c | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) (limited to 'drivers/mtd/nand/au1550nd.c') diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 275453ea7a71..31228334da12 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -40,6 +40,7 @@ static struct mtd_info *au1550_mtd = NULL; static void __iomem *p_nand; static int nand_width = 1; /* default x8 */ +static void (*au1550_write_byte)(struct mtd_info *, u_char); /* * Define partitions for flash device @@ -128,21 +129,6 @@ static u16 au_read_word(struct mtd_info *mtd) return ret; } -/** - * au_write_word - write one word to the chip - * @mtd: MTD device structure - * @word: data word to write - * - * write function for 16bit buswith without - * endianess conversion - */ -static void au_write_word(struct mtd_info *mtd, u16 word) -{ - struct nand_chip *this = mtd->priv; - writew(word, this->IO_ADDR_W); - au_sync(); -} - /** * au_write_buf - write buffer to chip * @mtd: MTD device structure @@ -379,9 +365,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i column -= 256; readcmd = NAND_CMD_READ1; } - this->write_byte(mtd, readcmd); + au1550_write_byte(mtd, readcmd); } - this->write_byte(mtd, command); + au1550_write_byte(mtd, command); /* Set ALE and clear CLE to start address cycle */ au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); @@ -394,10 +380,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i /* Adjust columns for 16 bit buswidth */ if (this->options & NAND_BUSWIDTH_16) column >>= 1; - this->write_byte(mtd, column); + au1550_write_byte(mtd, column); } if (page_addr != -1) { - this->write_byte(mtd, (u8)(page_addr & 0xff)); + au1550_write_byte(mtd, (u8)(page_addr & 0xff)); if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || @@ -415,11 +401,11 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i au1550_hwcontrol(mtd, NAND_CTL_SETNCE); } - this->write_byte(mtd, (u8)(page_addr >> 8)); + au1550_write_byte(mtd, (u8)(page_addr >> 8)); /* One more address cycle for devices > 32MiB */ if (this->chipsize > (32 << 20)) - this->write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); + au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); } /* Latch in address */ au1550_hwcontrol(mtd, NAND_CTL_CLRALE); @@ -597,8 +583,7 @@ static int __init au1xxx_nand_init(void) this->options |= NAND_BUSWIDTH_16; this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; - this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; - this->write_word = au_write_word; + au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; this->read_word = au_read_word; this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; -- cgit v1.2.3